]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI
authorKazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
Wed, 25 Jul 2018 09:10:21 +0000 (18:10 +0900)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 2 Apr 2019 08:08:20 +0000 (10:08 +0200)
According to the R-Car Gen3 Hardware Manual Rev. 1.00, and the RZ/G2
Hardware Manual Rev. 0.61, the parent clock of the EHCI/OHCI module
clocks on R-Car Gen3 and RZ/G2 SoCs is S3D2.

Signed-off-by: Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>
[takeshi: Update R-Car H3, M3-N, and E3]
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Update RZ/G2M and RZ/G2E]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
drivers/clk/renesas/r8a774a1-cpg-mssr.c
drivers/clk/renesas/r8a774c0-cpg-mssr.c
drivers/clk/renesas/r8a7795-cpg-mssr.c
drivers/clk/renesas/r8a7796-cpg-mssr.c
drivers/clk/renesas/r8a77965-cpg-mssr.c
drivers/clk/renesas/r8a77990-cpg-mssr.c

index 44161fd0a09caabaacdb949cb4f93b26f582eaa8..bce0e6d6d02c7e7b250802551a55b1343b88df9a 100644 (file)
@@ -165,8 +165,8 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
        DEF_MOD("vspd0",                 623,   R8A774A1_CLK_S0D2),
        DEF_MOD("vspb",                  626,   R8A774A1_CLK_S0D1),
        DEF_MOD("vspi0",                 631,   R8A774A1_CLK_S0D1),
-       DEF_MOD("ehci1",                 702,   R8A774A1_CLK_S3D4),
-       DEF_MOD("ehci0",                 703,   R8A774A1_CLK_S3D4),
+       DEF_MOD("ehci1",                 702,   R8A774A1_CLK_S3D2),
+       DEF_MOD("ehci0",                 703,   R8A774A1_CLK_S3D2),
        DEF_MOD("hsusb",                 704,   R8A774A1_CLK_S3D4),
        DEF_MOD("csi20",                 714,   R8A774A1_CLK_CSI0),
        DEF_MOD("csi40",                 716,   R8A774A1_CLK_CSI0),
index 57098b7e3d0eea3cfe029a2640014c9eef91d437..d095787f7d851fc9e57650404f6e074ad33cb474 100644 (file)
@@ -178,7 +178,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
        DEF_MOD("vspb",                  626,   R8A774C0_CLK_S0D1),
        DEF_MOD("vspi0",                 631,   R8A774C0_CLK_S0D1),
 
-       DEF_MOD("ehci0",                 703,   R8A774C0_CLK_S3D4),
+       DEF_MOD("ehci0",                 703,   R8A774C0_CLK_S3D2),
        DEF_MOD("hsusb",                 704,   R8A774C0_CLK_S3D4),
        DEF_MOD("csi40",                 716,   R8A774C0_CLK_CSI0),
        DEF_MOD("du1",                   723,   R8A774C0_CLK_S1D1),
index 8287816523c3c6021fede4d3eb799b555884cbd8..b9e42da38b72bdcb9a8e92983c6fa35928ac300a 100644 (file)
@@ -195,10 +195,10 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
        DEF_MOD("vspi2",                 629,   R8A7795_CLK_S2D1), /* ES1.x */
        DEF_MOD("vspi1",                 630,   R8A7795_CLK_S0D1),
        DEF_MOD("vspi0",                 631,   R8A7795_CLK_S0D1),
-       DEF_MOD("ehci3",                 700,   R8A7795_CLK_S3D4),
-       DEF_MOD("ehci2",                 701,   R8A7795_CLK_S3D4),
-       DEF_MOD("ehci1",                 702,   R8A7795_CLK_S3D4),
-       DEF_MOD("ehci0",                 703,   R8A7795_CLK_S3D4),
+       DEF_MOD("ehci3",                 700,   R8A7795_CLK_S3D2),
+       DEF_MOD("ehci2",                 701,   R8A7795_CLK_S3D2),
+       DEF_MOD("ehci1",                 702,   R8A7795_CLK_S3D2),
+       DEF_MOD("ehci0",                 703,   R8A7795_CLK_S3D2),
        DEF_MOD("hsusb",                 704,   R8A7795_CLK_S3D4),
        DEF_MOD("hsusb3",                705,   R8A7795_CLK_S3D4),
        DEF_MOD("csi21",                 713,   R8A7795_CLK_CSI0), /* ES1.x */
index 5cde1bff89235e90220ad97256ef1a9b2b9f7edc..97b58f13111441a819c27c8c71de6da1618c848b 100644 (file)
@@ -177,8 +177,8 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
        DEF_MOD("vspd0",                 623,   R8A7796_CLK_S0D2),
        DEF_MOD("vspb",                  626,   R8A7796_CLK_S0D1),
        DEF_MOD("vspi0",                 631,   R8A7796_CLK_S0D1),
-       DEF_MOD("ehci1",                 702,   R8A7796_CLK_S3D4),
-       DEF_MOD("ehci0",                 703,   R8A7796_CLK_S3D4),
+       DEF_MOD("ehci1",                 702,   R8A7796_CLK_S3D2),
+       DEF_MOD("ehci0",                 703,   R8A7796_CLK_S3D2),
        DEF_MOD("hsusb",                 704,   R8A7796_CLK_S3D4),
        DEF_MOD("csi20",                 714,   R8A7796_CLK_CSI0),
        DEF_MOD("csi40",                 716,   R8A7796_CLK_CSI0),
index fefa26a1a797d9a8c6bac1f4f7376713d39f28f8..ab25bd5f1371869e5c7883fd4e9081a65a93b6c4 100644 (file)
@@ -175,8 +175,8 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
        DEF_MOD("vspb",                 626,    R8A77965_CLK_S0D1),
        DEF_MOD("vspi0",                631,    R8A77965_CLK_S0D1),
 
-       DEF_MOD("ehci1",                702,    R8A77965_CLK_S3D4),
-       DEF_MOD("ehci0",                703,    R8A77965_CLK_S3D4),
+       DEF_MOD("ehci1",                702,    R8A77965_CLK_S3D2),
+       DEF_MOD("ehci0",                703,    R8A77965_CLK_S3D2),
        DEF_MOD("hsusb",                704,    R8A77965_CLK_S3D4),
        DEF_MOD("csi20",                714,    R8A77965_CLK_CSI0),
        DEF_MOD("csi40",                716,    R8A77965_CLK_CSI0),
index 99f602cb30a55913b70f1432bedcf572e248b7a8..3f22b8565648d5900eddaf9ac440c8044de2f682 100644 (file)
@@ -181,7 +181,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
        DEF_MOD("vspb",                  626,   R8A77990_CLK_S0D1),
        DEF_MOD("vspi0",                 631,   R8A77990_CLK_S0D1),
 
-       DEF_MOD("ehci0",                 703,   R8A77990_CLK_S3D4),
+       DEF_MOD("ehci0",                 703,   R8A77990_CLK_S3D2),
        DEF_MOD("hsusb",                 704,   R8A77990_CLK_S3D4),
        DEF_MOD("csi40",                 716,   R8A77990_CLK_CSI0),
        DEF_MOD("du1",                   723,   R8A77990_CLK_S1D1),