MIPS: R12000: Enable branch prediction global history

The R12000 added a new feature to enhance branch prediction called
"global history".  Per the Vr10000 Series User Manual (U10278EJ4V0UM),
Coprocessor 0, Diagnostic Register (22):

"""
If bit 26 is set, branch prediction uses all eight bits of the global
history register.  If bit 26 is not set, then bits 25:23 specify a count
of the number of bits of global history to be used. Thus if bits 26:23
are all zero, global history is disabled.

The global history contains a record of the taken/not-taken status of
recently executed branches, and when used is XOR'ed with the PC of a
branch being predicted to produce a hashed value for indexing the BPT.
Some programs with small "working set of conditional branches" benefit
significantly from the use of such hashing, some see slight performance
degradation.
"""

This patch enables global history on R12000 CPUs and up by setting bit
26 in the branch prediction diagnostic register (CP0 $22) to '1'.  Bits
25:23 are left alone so that all eight bits of the global history
register are available for branch prediction.

Signed-off-by: Joshua Kinard <kumba@gentoo.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 5aeaf19c26b0fa5db9282951d237fbe9738fc1f0..f25de771f7ed228478b54c6acbb559d1f36f46d0 100644 (file)
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -108,6 +108,9 @@
 #ifndef cpu_has_llsc
 #define cpu_has_llsc           (cpu_data[0].options & MIPS_CPU_LLSC)
 #endif
+#ifndef cpu_has_bp_ghist
+#define cpu_has_bp_ghist       (cpu_data[0].options & MIPS_CPU_BP_GHIST)
+#endif
 #ifndef kernel_uses_llsc
 #define kernel_uses_llsc       cpu_has_llsc
 #endif

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 73dd35787d1ae5dff6bfc93daf5bc1a37793c674..e46e40602af3cc0f584847d967d969b53985f775 100644 (file)
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -381,6 +381,7 @@ enum cpu_type_enum {
 #define MIPS_CPU_RW_LLB                0x1000000000ull /* LLADDR/LLB writes are allowed */
 #define MIPS_CPU_XPA           0x2000000000ull /* CPU supports Extended Physical Addressing */
 #define MIPS_CPU_CDMM          0x4000000000ull /* CPU has Common Device Memory Map */
+#define MIPS_CPU_BP_GHIST      0x8000000000ull /* R12K+ Branch Prediction Global History */
 
 /*
  * CPU ASE encodings

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 3b5a145af6593c16096a4d17c68d199a6d895e44..c5b0956a853027897716050e46be33006912e981 100644 (file)
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -707,6 +707,15 @@
 #define TX39_CONF_DRSIZE_SHIFT 0
 #define TX39_CONF_DRSIZE_MASK  0x00000003
 
+/*
+ * Interesting Bits in the R10K CP0 Branch Diagnostic Register
+ */
+/* Disable Branch Target Address Cache */
+#define R10K_DIAG_D_BTAC       (_ULCAST_(1) << 27)
+/* Enable Branch Prediction Global History */
+#define R10K_DIAG_E_GHIST      (_ULCAST_(1) << 26)
+/* Disable Branch Return Cache */
+#define R10K_DIAG_D_BRC                (_ULCAST_(1) << 22)
 
 /*
  * Coprocessor 1 (FPU) register names
@@ -1269,6 +1278,10 @@ do {                                                                     \
 #define read_c0_diag()         __read_32bit_c0_register($22, 0)
 #define write_c0_diag(val)     __write_32bit_c0_register($22, 0, val)
 
+/* R10K CP0 Branch Diagnostic register is 64bits wide */
+#define read_c0_r10k_diag()    __read_64bit_c0_register($22, 0)
+#define write_c0_r10k_diag(val)        __write_64bit_c0_register($22, 0, val)
+
 #define read_c0_diag1()                __read_32bit_c0_register($22, 1)
 #define write_c0_diag1(val)    __write_32bit_c0_register($22, 1, val)
 

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index f89eaa79785a6b55fdda93afffb150d248f1d483..dbe0792fc9c1bd99c4c452aa998d825662d55ec4 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -945,7 +945,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
                c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
                             MIPS_CPU_FPU | MIPS_CPU_32FPR |
                             MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
-                            MIPS_CPU_LLSC;
+                            MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
                c->tlbsize = 64;
                break;
        case PRID_IMP_R14000:
@@ -960,7 +960,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
                c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
                             MIPS_CPU_FPU | MIPS_CPU_32FPR |
                             MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
-                            MIPS_CPU_LLSC;
+                            MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
                c->tlbsize = 64;
                break;
        case PRID_IMP_LOONGSON_64:  /* Loongson-2/3 */
@@ -1480,6 +1480,10 @@ void cpu_probe(void)
        else
                cpu_set_nofpu_opts(c);
 
+       if (cpu_has_bp_ghist)
+               write_c0_r10k_diag(read_c0_r10k_diag() |
+                                  R10K_DIAG_E_GHIST);
+
        if (cpu_has_mips_r2_r6) {
                c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
                /* R2 has Performance Counter Interrupt indicator */