]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
dt-bindings: ARM: sunxi: Document A80 SoC secure SRAM usage by SMP hotplug
authorChen-Yu Tsai <wens@csie.org>
Wed, 17 Jan 2018 08:46:52 +0000 (16:46 +0800)
committerChen-Yu Tsai <wens@csie.org>
Tue, 20 Feb 2018 03:12:39 +0000 (11:12 +0800)
On the Allwinner A80 SoC the BROM supports hotplugging the primary core
(cpu0) by checking two 32bit values at a specific location within the
secure SRAM block. This region needs to be reserved and accessible to
the SMP code.

Document its usage.

Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Documentation/devicetree/bindings/arm/sunxi/smp-sram.txt [new file with mode: 0644]

diff --git a/Documentation/devicetree/bindings/arm/sunxi/smp-sram.txt b/Documentation/devicetree/bindings/arm/sunxi/smp-sram.txt
new file mode 100644 (file)
index 0000000..082e6a9
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+Allwinner SRAM for smp bringup:
+------------------------------------------------
+
+Allwinner's A80 SoC uses part of the secure sram for hotplugging of the
+primary core (cpu0). Once the core gets powered up it checks if a magic
+value is set at a specific location. If it is then the BROM will jump
+to the software entry address, instead of executing a standard boot.
+
+Therefore a reserved section sub-node has to be added to the mmio-sram
+declaration.
+
+Note that this is separate from the Allwinner SRAM controller found in
+../../sram/sunxi-sram.txt. This SRAM is secure only and not mappable to
+any device.
+
+Also there are no "secure-only" properties. The implementation should
+check if this SRAM is usable first.
+
+Required sub-node properties:
+- compatible : depending on the SoC this should be one of:
+               "allwinner,sun9i-a80-smp-sram"
+
+The rest of the properties should follow the generic mmio-sram discription
+found in ../../misc/sram.txt
+
+Example:
+
+       sram_b: sram@20000 {
+               /* 256 KiB secure SRAM at 0x20000 */
+               compatible = "mmio-sram";
+               reg = <0x00020000 0x40000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0x00020000 0x40000>;
+
+               smp-sram@1000 {
+                       /*
+                        * This is checked by BROM to determine if
+                        * cpu0 should jump to SMP entry vector
+                        */
+                       compatible = "allwinner,sun9i-a80-smp-sram";
+                       reg = <0x1000 0x8>;
+               };
+       };