}
espi_trans->tx_buf = local_buf;
--- - espi_trans->rx_buf = local_buf + espi_trans->n_tx;
+++ + espi_trans->rx_buf = local_buf;
fsl_espi_do_trans(m, espi_trans);
espi_trans->actual_length = espi_trans->len;
espi_trans->n_rx = trans_len;
espi_trans->len = trans_len + n_tx;
espi_trans->tx_buf = local_buf;
--- - espi_trans->rx_buf = local_buf + n_tx;
+++ + espi_trans->rx_buf = local_buf;
fsl_espi_do_trans(m, espi_trans);
memcpy(rx_buf + pos, espi_trans->rx_buf + n_tx, trans_len);
return -EINVAL;
if (!cs) {
-- -- cs = kzalloc(sizeof *cs, GFP_KERNEL);
++ ++ cs = devm_kzalloc(&spi->dev, sizeof(*cs), GFP_KERNEL);
if (!cs)
return -ENOMEM;
spi->controller_state = cs;
struct spi_master *master;
struct mpc8xxx_spi *mpc8xxx_spi;
struct fsl_espi_reg *reg_base;
--- - u32 regval;
--- - int i, ret = 0;
+++ + struct device_node *nc;
+++ + const __be32 *prop;
+++ + u32 regval, csmode;
+++ + int i, len, ret = 0;
master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
if (!master) {
mpc8xxx_spi_write_reg(®_base->event, 0xffffffff);
/* Init eSPI CS mode register */
--- - for (i = 0; i < pdata->max_chipselect; i++)
--- - mpc8xxx_spi_write_reg(®_base->csmode[i], CSMODE_INIT_VAL);
+++ + for_each_available_child_of_node(master->dev.of_node, nc) {
+++ + /* get chip select */
+++ + prop = of_get_property(nc, "reg", &len);
+++ + if (!prop || len < sizeof(*prop))
+++ + continue;
+++ + i = be32_to_cpup(prop);
+++ + if (i < 0 || i >= pdata->max_chipselect)
+++ + continue;
+++ +
+++ + csmode = CSMODE_INIT_VAL;
+++ + /* check if CSBEF is set in device tree */
+++ + prop = of_get_property(nc, "fsl,csbef", &len);
+++ + if (prop && len >= sizeof(*prop)) {
+++ + csmode &= ~(CSMODE_BEF(0xf));
+++ + csmode |= CSMODE_BEF(be32_to_cpup(prop));
+++ + }
+++ + /* check if CSAFT is set in device tree */
+++ + prop = of_get_property(nc, "fsl,csaft", &len);
+++ + if (prop && len >= sizeof(*prop)) {
+++ + csmode &= ~(CSMODE_AFT(0xf));
+++ + csmode |= CSMODE_AFT(be32_to_cpup(prop));
+++ + }
+++ + mpc8xxx_spi_write_reg(®_base->csmode[i], csmode);
+++ +
+++ + dev_info(dev, "cs=%d, init_csmode=0x%x\n", i, csmode);
+++ + }
/* Enable SPI interface */
regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
writel_relaxed(opflags, controller->base + QUP_OPERATIONAL);
if (!xfer) {
---- dev_err_ratelimited(controller->dev, "unexpected irq %x08 %x08 %x08\n",
++++ dev_err_ratelimited(controller->dev, "unexpected irq %08x %08x %08x\n",
qup_err, spi_err, opflags);
return IRQ_HANDLED;
}
n_words = xfer->len / w_size;
controller->w_size = w_size;
---- if (n_words <= controller->in_fifo_sz) {
++++ if (n_words <= (controller->in_fifo_sz / sizeof(u32))) {
mode = QUP_IO_M_MODE_FIFO;
writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT);
writel_relaxed(n_words, controller->base + QUP_MX_WRITE_CNT);
int ret;
ret = pm_runtime_get_sync(&pdev->dev);
---- if (ret)
++++ if (ret < 0)
return ret;
ret = spi_qup_set_state(controller, QUP_STATE_RESET);
return 0;
}
---- static struct of_device_id spi_qup_dt_match[] = {
++++ static const struct of_device_id spi_qup_dt_match[] = {
{ .compatible = "qcom,spi-qup-v2.1.1", },
{ .compatible = "qcom,spi-qup-v2.2.1", },
{ }