]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
drm/etnaviv: add RA perf domain
authorChristian Gmeiner <christian.gmeiner@gmail.com>
Sun, 24 Sep 2017 13:15:36 +0000 (15:15 +0200)
committerLucas Stach <l.stach@pengutronix.de>
Tue, 10 Oct 2017 09:45:51 +0000 (11:45 +0200)
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
drivers/gpu/drm/etnaviv/etnaviv_perfmon.c

index 5dbd5b433dc38b0520dea048d9f7a5e0f0f4b2bf..aa7fe0b954a101b9d79b45f6bd2f03d89a7772c4 100644 (file)
@@ -256,6 +256,49 @@ static const struct etnaviv_pm_domain doms_3d[] = {
                                &perf_reg_read
                        }
                }
+       },
+       {
+               .name = "RA",
+               .profile_read = VIVS_MC_PROFILE_RA_READ,
+               .profile_config = VIVS_MC_PROFILE_CONFIG1,
+               .nr_signals = 7,
+               .signal = (const struct etnaviv_pm_signal[]) {
+                       {
+                               "VALID_PIXEL_COUNT",
+                               VIVS_MC_PROFILE_CONFIG1_RA_VALID_PIXEL_COUNT,
+                               &perf_reg_read
+                       },
+                       {
+                               "TOTAL_QUAD_COUNT",
+                               VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_QUAD_COUNT,
+                               &perf_reg_read
+                       },
+                       {
+                               "VALID_QUAD_COUNT_AFTER_EARLY_Z",
+                               VIVS_MC_PROFILE_CONFIG1_RA_VALID_QUAD_COUNT_AFTER_EARLY_Z,
+                               &perf_reg_read
+                       },
+                       {
+                               "TOTAL_PRIMITIVE_COUNT",
+                               VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_PRIMITIVE_COUNT,
+                               &perf_reg_read
+                       },
+                       {
+                               "PIPE_CACHE_MISS_COUNTER",
+                               VIVS_MC_PROFILE_CONFIG1_RA_PIPE_CACHE_MISS_COUNTER,
+                               &perf_reg_read
+                       },
+                       {
+                               "PREFETCH_CACHE_MISS_COUNTER",
+                               VIVS_MC_PROFILE_CONFIG1_RA_PREFETCH_CACHE_MISS_COUNTER,
+                               &perf_reg_read
+                       },
+                       {
+                               "CULLED_QUAD_COUNT",
+                               VIVS_MC_PROFILE_CONFIG1_RA_CULLED_QUAD_COUNT,
+                               &perf_reg_read
+                       }
+               }
        }
 };