drm/i915/tgl: Move fault registers to their new offset

The fault registers moved to another offset. The old location is now
taken by the global MOCS registers, to be added in a follow up change.

Based on previous patches by Michel Thierry <michel.thierry@intel.com>.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190730180407.5993-2-lucas.demarchi@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index f7e69db4019d0544652eaf93f1e26458486b08f4..caa07eb20a64475eaa269a593683d12ec39b5ef4 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -79,7 +79,10 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
                                   I915_MASTER_ERROR_INTERRUPT);
        }
 
-       if (INTEL_GEN(i915) >= 8) {
+       if (INTEL_GEN(i915) >= 12) {
+               rmw_clear(uncore, GEN12_RING_FAULT_REG, RING_FAULT_VALID);
+               intel_uncore_posting_read(uncore, GEN12_RING_FAULT_REG);
+       } else if (INTEL_GEN(i915) >= 8) {
                rmw_clear(uncore, GEN8_RING_FAULT_REG, RING_FAULT_VALID);
                intel_uncore_posting_read(uncore, GEN8_RING_FAULT_REG);
        } else if (INTEL_GEN(i915) >= 6) {
@@ -117,14 +120,27 @@ static void gen6_check_faults(struct intel_gt *gt)
 static void gen8_check_faults(struct intel_gt *gt)
 {
        struct intel_uncore *uncore = gt->uncore;
-       u32 fault = intel_uncore_read(uncore, GEN8_RING_FAULT_REG);
+       i915_reg_t fault_reg, fault_data0_reg, fault_data1_reg;
+       u32 fault;
+
+       if (INTEL_GEN(gt->i915) >= 12) {
+               fault_reg = GEN12_RING_FAULT_REG;
+               fault_data0_reg = GEN12_FAULT_TLB_DATA0;
+               fault_data1_reg = GEN12_FAULT_TLB_DATA1;
+       } else {
+               fault_reg = GEN8_RING_FAULT_REG;
+               fault_data0_reg = GEN8_FAULT_TLB_DATA0;
+               fault_data1_reg = GEN8_FAULT_TLB_DATA1;
+       }
 
+       fault = intel_uncore_read(uncore, fault_reg);
        if (fault & RING_FAULT_VALID) {
                u32 fault_data0, fault_data1;
                u64 fault_addr;
 
-               fault_data0 = intel_uncore_read(uncore, GEN8_FAULT_TLB_DATA0);
-               fault_data1 = intel_uncore_read(uncore, GEN8_FAULT_TLB_DATA1);
+               fault_data0 = intel_uncore_read(uncore, fault_data0_reg);
+               fault_data1 = intel_uncore_read(uncore, fault_data1_reg);
+
                fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
                             ((u64)fault_data0 << 12);
 

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 674d341a23f65851fd259ca56b81507d56784e0c..6b9072c5151c6eda0d2e82e86791412e4e98bb02 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1106,7 +1106,10 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
 
        if (INTEL_GEN(dev_priv) >= 6) {
                ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL);
-               if (INTEL_GEN(dev_priv) >= 8)
+
+               if (INTEL_GEN(dev_priv) >= 12)
+                       ee->fault_reg = I915_READ(GEN12_RING_FAULT_REG);
+               else if (INTEL_GEN(dev_priv) >= 8)
                        ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG);
                else
                        ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine);
@@ -1541,7 +1544,12 @@ static void capture_reg_state(struct i915_gpu_state *error)
        if (IS_GEN(i915, 7))
                error->err_int = intel_uncore_read(uncore, GEN7_ERR_INT);
 
-       if (INTEL_GEN(i915) >= 8) {
+       if (INTEL_GEN(i915) >= 12) {
+               error->fault_data0 = intel_uncore_read(uncore,
+                                                      GEN12_FAULT_TLB_DATA0);
+               error->fault_data1 = intel_uncore_read(uncore,
+                                                      GEN12_FAULT_TLB_DATA1);
+       } else if (INTEL_GEN(i915) >= 8) {
                error->fault_data0 = intel_uncore_read(uncore,
                                                       GEN8_FAULT_TLB_DATA0);
                error->fault_data1 = intel_uncore_read(uncore,

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 21306dd3790aa4b0a86164976aa2c8e2d13259fc..80e98ec99410ada7480223a194576233958a4e19 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2490,6 +2490,7 @@ enum i915_power_well_id {
 #define RENDER_HWS_PGA_GEN7    _MMIO(0x04080)
 #define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 * (engine)->hw_id)
 #define GEN8_RING_FAULT_REG    _MMIO(0x4094)
+#define GEN12_RING_FAULT_REG   _MMIO(0xcec4)
 #define   GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
 #define   RING_FAULT_GTTSEL_MASK (1 << 11)
 #define   RING_FAULT_SRCID(x)  (((x) >> 3) & 0xff)
@@ -2633,6 +2634,8 @@ enum i915_power_well_id {
 
 #define GEN8_FAULT_TLB_DATA0           _MMIO(0x4b10)
 #define GEN8_FAULT_TLB_DATA1           _MMIO(0x4b14)
+#define GEN12_FAULT_TLB_DATA0          _MMIO(0xceb8)
+#define GEN12_FAULT_TLB_DATA1          _MMIO(0xcebc)
 #define   FAULT_VA_HIGH_BITS           (0xf << 0)
 #define   FAULT_GTT_SEL                        (1 << 4)