net/mlx5: Read MCAM register groups 1 and 2

On load, Driver caches MCAM (Management Capabilities Mask Register)
registers. in addition to the only MCAM register group (0) the driver
already reads, here we add support for reading groups 1 and 2.

Signed-off-by: Eran Ben Elisha <eranbe@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw.c b/drivers/net/ethernet/mellanox/mlx5/core/fw.c
index c375edfe528c7ab026341b56e5bf4a06b6783bda..d89ff1d0911951a541daf069412ae2ebe498479c 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/fw.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/fw.c
@@ -131,11 +131,11 @@ static int mlx5_get_pcam_reg(struct mlx5_core_dev *dev)
                                   MLX5_PCAM_REGS_5000_TO_507F);
 }
 
-static int mlx5_get_mcam_reg(struct mlx5_core_dev *dev)
+static int mlx5_get_mcam_access_reg_group(struct mlx5_core_dev *dev,
+                                         enum mlx5_mcam_reg_groups group)
 {
-       return mlx5_query_mcam_reg(dev, dev->caps.mcam,
-                                  MLX5_MCAM_FEATURE_ENHANCED_FEATURES,
-                                  MLX5_MCAM_REGS_FIRST_128);
+       return mlx5_query_mcam_reg(dev, dev->caps.mcam[group],
+                                  MLX5_MCAM_FEATURE_ENHANCED_FEATURES, group);
 }
 
 static int mlx5_get_qcam_reg(struct mlx5_core_dev *dev)
@@ -221,8 +221,11 @@ int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
        if (MLX5_CAP_GEN(dev, pcam_reg))
                mlx5_get_pcam_reg(dev);
 
-       if (MLX5_CAP_GEN(dev, mcam_reg))
-               mlx5_get_mcam_reg(dev);
+       if (MLX5_CAP_GEN(dev, mcam_reg)) {
+               mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_FIRST_128);
+               mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_0x9080_0x90FF);
+               mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_0x9100_0x917F);
+       }
 
        if (MLX5_CAP_GEN(dev, qcam_reg))
                mlx5_get_qcam_reg(dev);

diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h
index 1a1c53f0262d4505daebc4d8213acc10eb597054..0e62c3db45e5ce7a26298397b4e94d5ecda71dd7 100644 (file)
--- a/include/linux/mlx5/device.h
+++ b/include/linux/mlx5/device.h
@@ -1121,6 +1121,9 @@ enum mlx5_pcam_feature_groups {
 
 enum mlx5_mcam_reg_groups {
        MLX5_MCAM_REGS_FIRST_128                    = 0x0,
+       MLX5_MCAM_REGS_0x9080_0x90FF                = 0x1,
+       MLX5_MCAM_REGS_0x9100_0x917F                = 0x2,
+       MLX5_MCAM_REGS_NUM                          = 0x3,
 };
 
 enum mlx5_mcam_feature_groups {
@@ -1269,7 +1272,16 @@ enum mlx5_qcam_feature_groups {
        MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
 
 #define MLX5_CAP_MCAM_REG(mdev, reg) \
-       MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)
+       MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_FIRST_128], \
+                mng_access_reg_cap_mask.access_regs.reg)
+
+#define MLX5_CAP_MCAM_REG1(mdev, reg) \
+       MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9080_0x90FF], \
+                mng_access_reg_cap_mask.access_regs1.reg)
+
+#define MLX5_CAP_MCAM_REG2(mdev, reg) \
+       MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9100_0x917F], \
+                mng_access_reg_cap_mask.access_regs2.reg)
 
 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
        MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)

diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h
index 27200dea029776a20c64468a1ed2a4125edd1a67..54431256af42894f19d22aad780ec7b3e64ef3f2 100644 (file)
--- a/include/linux/mlx5/driver.h
+++ b/include/linux/mlx5/driver.h
@@ -684,7 +684,7 @@ struct mlx5_core_dev {
                u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
                u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
                u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
-               u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
+               u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
                u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
                u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
                u8  embedded_cpu;