dmaengine: dw: Don't pollute CTL_LO on iDMA 32-bit

Intel iDMA 32-bit doesn't have a concept of bus masters and thus
there is no need to setup any kind of masters in the CTL_LO register.

Moreover, the burst size for memory-to-memory transfer is not what is says,
we need to have a corrected list of possible sizes. Note, that
the size of 8 items, each of that up to 4 bytes, is chosen because of
maximum of 1/2 FIFO, which is 64 bytes on Intel Merrifield.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index 6a23203e601da6ed840439423bd5981c7bff6d4a..b7e4dab28f8a0af28df653c7661eaa56d8db11c6 100644 (file)
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c
@@ -37,27 +37,6 @@
  * support descriptor writeback.
  */
 
-#define DWC_DEFAULT_CTLLO(_chan) ({                            \
-               struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan);       \
-               struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
-               bool _is_slave = is_slave_direction(_dwc->direction);   \
-               u8 _smsize = _is_slave ? _sconfig->src_maxburst :       \
-                       DW_DMA_MSIZE_16;                        \
-               u8 _dmsize = _is_slave ? _sconfig->dst_maxburst :       \
-                       DW_DMA_MSIZE_16;                        \
-               u8 _dms = (_dwc->direction == DMA_MEM_TO_DEV) ?         \
-                       _dwc->dws.p_master : _dwc->dws.m_master;        \
-               u8 _sms = (_dwc->direction == DMA_DEV_TO_MEM) ?         \
-                       _dwc->dws.p_master : _dwc->dws.m_master;        \
-                                                               \
-               (DWC_CTLL_DST_MSIZE(_dmsize)                    \
-                | DWC_CTLL_SRC_MSIZE(_smsize)                  \
-                | DWC_CTLL_LLP_D_EN                            \
-                | DWC_CTLL_LLP_S_EN                            \
-                | DWC_CTLL_DMS(_dms)                           \
-                | DWC_CTLL_SMS(_sms));                         \
-       })
-
 /* The set of bus widths supported by the DMA controller */
 #define DW_DMA_BUSWIDTHS                         \
        BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED)       | \
@@ -596,7 +575,7 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 
        src_width = dst_width = __ffs(data_width | src | dest | len);
 
-       ctllo = DWC_DEFAULT_CTLLO(chan)
+       ctllo = dw->prepare_ctllo(dwc)
                        | DWC_CTLL_DST_WIDTH(dst_width)
                        | DWC_CTLL_SRC_WIDTH(src_width)
                        | DWC_CTLL_DST_INC
@@ -676,10 +655,10 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
        case DMA_MEM_TO_DEV:
                reg_width = __ffs(sconfig->dst_addr_width);
                reg = sconfig->dst_addr;
-               ctllo = (DWC_DEFAULT_CTLLO(chan)
+               ctllo = dw->prepare_ctllo(dwc)
                                | DWC_CTLL_DST_WIDTH(reg_width)
                                | DWC_CTLL_DST_FIX
-                               | DWC_CTLL_SRC_INC);
+                               | DWC_CTLL_SRC_INC;
 
                ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
                        DWC_CTLL_FC(DW_DMA_FC_D_M2P);
@@ -726,10 +705,10 @@ dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
        case DMA_DEV_TO_MEM:
                reg_width = __ffs(sconfig->src_addr_width);
                reg = sconfig->src_addr;
-               ctllo = (DWC_DEFAULT_CTLLO(chan)
+               ctllo = dw->prepare_ctllo(dwc)
                                | DWC_CTLL_SRC_WIDTH(reg_width)
                                | DWC_CTLL_DST_INC
-                               | DWC_CTLL_SRC_FIX);
+                               | DWC_CTLL_SRC_FIX;
 
                ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
                        DWC_CTLL_FC(DW_DMA_FC_D_P2M);

diff --git a/drivers/dma/dw/dw.c b/drivers/dma/dw/dw.c
index 156088f768f24bf2d4506a6a54aaeb1b4546f29a..7a085b3c1854cd6d6188160e420ea320268649d2 100644 (file)
--- a/drivers/dma/dw/dw.c
+++ b/drivers/dma/dw/dw.c
@@ -4,6 +4,7 @@
 // Copyright (C) 2013,2018 Intel Corporation
 
 #include <linux/bitops.h>
+#include <linux/dmaengine.h>
 #include <linux/errno.h>
 #include <linux/slab.h>
 #include <linux/types.h>
@@ -63,6 +64,22 @@ static size_t dw_dma_block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width)
        return DWC_CTLH_BLOCK_TS(block) << width;
 }
 
+static u32 dw_dma_prepare_ctllo(struct dw_dma_chan *dwc)
+{
+       struct dma_slave_config *sconfig = &dwc->dma_sconfig;
+       bool is_slave = is_slave_direction(dwc->direction);
+       u8 smsize = is_slave ? sconfig->src_maxburst : DW_DMA_MSIZE_16;
+       u8 dmsize = is_slave ? sconfig->dst_maxburst : DW_DMA_MSIZE_16;
+       u8 p_master = dwc->dws.p_master;
+       u8 m_master = dwc->dws.m_master;
+       u8 dms = (dwc->direction == DMA_MEM_TO_DEV) ? p_master : m_master;
+       u8 sms = (dwc->direction == DMA_DEV_TO_MEM) ? p_master : m_master;
+
+       return DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN |
+              DWC_CTLL_DST_MSIZE(dmsize) | DWC_CTLL_SRC_MSIZE(smsize) |
+              DWC_CTLL_DMS(dms) | DWC_CTLL_SMS(sms);
+}
+
 static void dw_dma_encode_maxburst(struct dw_dma_chan *dwc, u32 *maxburst)
 {
        /*
@@ -99,6 +116,7 @@ int dw_dma_probe(struct dw_dma_chip *chip)
        dw->initialize_chan = dw_dma_initialize_chan;
        dw->suspend_chan = dw_dma_suspend_chan;
        dw->resume_chan = dw_dma_resume_chan;
+       dw->prepare_ctllo = dw_dma_prepare_ctllo;
        dw->encode_maxburst = dw_dma_encode_maxburst;
        dw->bytes2block = dw_dma_bytes2block;
        dw->block2bytes = dw_dma_block2bytes;

diff --git a/drivers/dma/dw/idma32.c b/drivers/dma/dw/idma32.c
index cd23b9238333fd8a48ee42b9a708a8b9c157ac0f..f006573088110508a1e239a18e9e67af933f2070 100644 (file)
--- a/drivers/dma/dw/idma32.c
+++ b/drivers/dma/dw/idma32.c
@@ -2,6 +2,7 @@
 // Copyright (C) 2013,2018 Intel Corporation
 
 #include <linux/bitops.h>
+#include <linux/dmaengine.h>
 #include <linux/errno.h>
 #include <linux/slab.h>
 #include <linux/types.h>
@@ -69,6 +70,17 @@ static size_t idma32_block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width)
        return IDMA32C_CTLH_BLOCK_TS(block);
 }
 
+static u32 idma32_prepare_ctllo(struct dw_dma_chan *dwc)
+{
+       struct dma_slave_config *sconfig = &dwc->dma_sconfig;
+       bool is_slave = is_slave_direction(dwc->direction);
+       u8 smsize = is_slave ? sconfig->src_maxburst : IDMA32_MSIZE_8;
+       u8 dmsize = is_slave ? sconfig->dst_maxburst : IDMA32_MSIZE_8;
+
+       return DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN |
+              DWC_CTLL_DST_MSIZE(dmsize) | DWC_CTLL_SRC_MSIZE(smsize);
+}
+
 static void idma32_encode_maxburst(struct dw_dma_chan *dwc, u32 *maxburst)
 {
        *maxburst = *maxburst > 1 ? fls(*maxburst) - 1 : 0;
@@ -126,6 +138,7 @@ int idma32_dma_probe(struct dw_dma_chip *chip)
        dw->initialize_chan = idma32_initialize_chan;
        dw->suspend_chan = idma32_suspend_chan;
        dw->resume_chan = idma32_resume_chan;
+       dw->prepare_ctllo = idma32_prepare_ctllo;
        dw->encode_maxburst = idma32_encode_maxburst;
        dw->bytes2block = idma32_bytes2block;
        dw->block2bytes = idma32_block2bytes;

diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h
index 6cf299facf4588ae0a4423c20aff17c743297d24..07f91325e5596ff9504260d71ae6a2ff61396eb7 100644 (file)
--- a/drivers/dma/dw/regs.h
+++ b/drivers/dma/dw/regs.h
@@ -222,6 +222,16 @@ enum dw_dma_msize {
 
 /* iDMA 32-bit support */
 
+/* bursts size */
+enum idma32_msize {
+       IDMA32_MSIZE_1,
+       IDMA32_MSIZE_2,
+       IDMA32_MSIZE_4,
+       IDMA32_MSIZE_8,
+       IDMA32_MSIZE_16,
+       IDMA32_MSIZE_32,
+};
+
 /* Bitfields in CTL_HI */
 #define IDMA32C_CTLH_BLOCK_TS_MASK     GENMASK(16, 0)
 #define IDMA32C_CTLH_BLOCK_TS(x)       ((x) & IDMA32C_CTLH_BLOCK_TS_MASK)
@@ -316,6 +326,7 @@ struct dw_dma {
        void    (*initialize_chan)(struct dw_dma_chan *dwc);
        void    (*suspend_chan)(struct dw_dma_chan *dwc, bool drain);
        void    (*resume_chan)(struct dw_dma_chan *dwc, bool drain);
+       u32     (*prepare_ctllo)(struct dw_dma_chan *dwc);
        void    (*encode_maxburst)(struct dw_dma_chan *dwc, u32 *maxburst);
        u32     (*bytes2block)(struct dw_dma_chan *dwc, size_t bytes,
                               unsigned int width, size_t *len);