spi: zynq-qspi: Keep the bitfields naming consistent

Most of the bits/bitfields #define'd in this driver are composed with:
1/ the driver prefix
2/ the name of the register they apply to

Keep the naming consistent by applying this rule to the CONFIG register
internals. These definitions will be used in a following change set.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/r/20191108140744.1734-4-miquel.raynal@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-zynq-qspi.c b/drivers/spi/spi-zynq-qspi.c
index 9f53ea08adf7abf97756870a21817437c86f0e1f..530533b6c974d299bf72e82434a6423f402b3104 100644 (file)
--- a/drivers/spi/spi-zynq-qspi.c
+++ b/drivers/spi/spi-zynq-qspi.c
@@ -60,9 +60,9 @@
  * These are the values used in the calculation of baud rate divisor and
  * setting the slave select.
  */
-#define ZYNQ_QSPI_BAUD_DIV_MAX         GENMASK(2, 0) /* Baud rate maximum */
-#define ZYNQ_QSPI_BAUD_DIV_SHIFT       3 /* Baud rate divisor shift in CR */
-#define ZYNQ_QSPI_SS_SHIFT             10 /* Slave Select field shift in CR */
+#define ZYNQ_QSPI_CONFIG_BAUD_DIV_MAX  GENMASK(2, 0) /* Baud rate maximum */
+#define ZYNQ_QSPI_CONFIG_BAUD_DIV_SHIFT        3 /* Baud rate divisor shift */
+#define ZYNQ_QSPI_CONFIG_PCS           10 /* Peripheral Chip Select */
 
 /*
  * QSPI Interrupt Registers bit Masks
@@ -292,7 +292,7 @@ static void zynq_qspi_chipselect(struct spi_device *spi, bool assert)
                /* Select the slave */
                config_reg &= ~ZYNQ_QSPI_CONFIG_SSCTRL_MASK;
                config_reg |= (((~(BIT(spi->chip_select))) <<
-                               ZYNQ_QSPI_SS_SHIFT) &
+                               ZYNQ_QSPI_CONFIG_PCS) &
                                ZYNQ_QSPI_CONFIG_SSCTRL_MASK);
        } else {
                config_reg |= ZYNQ_QSPI_CONFIG_SSCTRL_MASK;
@@ -331,7 +331,7 @@ static int zynq_qspi_config_op(struct zynq_qspi *xqspi, struct spi_device *spi)
         *      ----------------
         *      111 - divide by 256
         */
-       while ((baud_rate_val < ZYNQ_QSPI_BAUD_DIV_MAX)  &&
+       while ((baud_rate_val < ZYNQ_QSPI_CONFIG_BAUD_DIV_MAX)  &&
               (clk_get_rate(xqspi->refclk) / (2 << baud_rate_val)) >
                spi->max_speed_hz)
                baud_rate_val++;
@@ -347,7 +347,7 @@ static int zynq_qspi_config_op(struct zynq_qspi *xqspi, struct spi_device *spi)
                config_reg |= ZYNQ_QSPI_CONFIG_CPOL_MASK;
 
        config_reg &= ~ZYNQ_QSPI_CONFIG_BDRATE_MASK;
-       config_reg |= (baud_rate_val << ZYNQ_QSPI_BAUD_DIV_SHIFT);
+       config_reg |= (baud_rate_val << ZYNQ_QSPI_CONFIG_BAUD_DIV_SHIFT);
        zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);
 
        return 0;