]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
usb: mtu3: enable SETUPENDISR interrupt
authorChunfeng Yun <chunfeng.yun@mediatek.com>
Thu, 29 Nov 2018 02:34:35 +0000 (10:34 +0800)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 5 Dec 2018 09:14:06 +0000 (10:14 +0100)
If the controller receives a new SETUP during SETUP data stage,
and will generate SETUPENDISR interrupt, the driver should abort
the current SETUP command and process the new one.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/usb/mtu3/mtu3_core.c
drivers/usb/mtu3/mtu3_gadget_ep0.c
drivers/usb/mtu3/mtu3_hw_regs.h

index 1ffc0bc31c1d042b50e3522f2ffc536c0e971925..b6b20949d63a1a0453680e46ff564647cd14b850 100644 (file)
@@ -484,7 +484,7 @@ void mtu3_ep0_setup(struct mtu3 *mtu)
        mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr);
 
        /* Enable EP0 interrupt */
-       mtu3_writel(mtu->mac_base, U3D_EPIESR, EP0ISR);
+       mtu3_writel(mtu->mac_base, U3D_EPIESR, EP0ISR | SETUPENDISR);
 }
 
 static int mtu3_mem_alloc(struct mtu3 *mtu)
index 3c464d8ae023fa4eb6d28ef1f6a9db47f369551e..7cb7ac9804460038f5b229037cc10a26ac240fa2 100644 (file)
@@ -692,9 +692,13 @@ irqreturn_t mtu3_ep0_isr(struct mtu3 *mtu)
        mtu3_writel(mbase, U3D_EPISR, int_status); /* W1C */
 
        /* only handle ep0's */
-       if (!(int_status & EP0ISR))
+       if (!(int_status & (EP0ISR | SETUPENDISR)))
                return IRQ_NONE;
 
+       /* abort current SETUP, and process new one */
+       if (int_status & SETUPENDISR)
+               mtu->ep0_state = MU3D_EP0_STATE_SETUP;
+
        csr = mtu3_readl(mbase, U3D_EP0CSR);
 
        dev_dbg(mtu->dev, "%s csr=0x%x\n", __func__, csr);
index a45bb253939f2c8e1a85c1e7ee7b84ad3f0182a5..d11fcd64c19df9feedfa516e2a66135d5338dbce 100644 (file)
 
 /* U3D_EPISR */
 #define EPRISR(x)              (BIT(16) << (x))
+#define SETUPENDISR            BIT(16)
 #define EPTISR(x)              (BIT(0) << (x))
 #define EP0ISR                 BIT(0)