arm: dts: mt7623: add afe nodes to the mt7623.dtsi file

Add afe nodes to the mt7623.dtsi file. Which
is the necessary node for I2S audio in/out.

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index 95c6fca0738ee85c57aaade141e4b35b7904adc7..5ed9821099c21a7840d2b1f72b4c28042531b13f 100644 (file)
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -378,6 +378,105 @@ bch: ecc@1100e000 {
                status = "disabled";
        };
 
+       afe: audio-controller@11220000 {
+               compatible = "mediatek,mt7623-audio",
+                            "mediatek,mt2701-audio";
+               reg = <0 0x11220000 0 0x2000>,
+                     <0 0x112a0000 0 0x20000>;
+               interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
+               power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
+
+               clocks = <&infracfg CLK_INFRA_AUDIO>,
+                        <&topckgen CLK_TOP_AUD_MUX1_SEL>,
+                        <&topckgen CLK_TOP_AUD_MUX2_SEL>,
+                        <&topckgen CLK_TOP_AUD_MUX1_DIV>,
+                        <&topckgen CLK_TOP_AUD_MUX2_DIV>,
+                        <&topckgen CLK_TOP_AUD_48K_TIMING>,
+                        <&topckgen CLK_TOP_AUD_44K_TIMING>,
+                        <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
+                        <&topckgen CLK_TOP_APLL_SEL>,
+                        <&topckgen CLK_TOP_AUD1PLL_98M>,
+                        <&topckgen CLK_TOP_AUD2PLL_90M>,
+                        <&topckgen CLK_TOP_HADDS2PLL_98M>,
+                        <&topckgen CLK_TOP_HADDS2PLL_294M>,
+                        <&topckgen CLK_TOP_AUDPLL>,
+                        <&topckgen CLK_TOP_AUDPLL_D4>,
+                        <&topckgen CLK_TOP_AUDPLL_D8>,
+                        <&topckgen CLK_TOP_AUDPLL_D16>,
+                        <&topckgen CLK_TOP_AUDPLL_D24>,
+                        <&topckgen CLK_TOP_AUDINTBUS_SEL>,
+                        <&clk26m>,
+                        <&topckgen CLK_TOP_SYSPLL1_D4>,
+                        <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
+                        <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
+                        <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
+                        <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
+                        <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
+                        <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
+                        <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
+                        <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
+                        <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
+                        <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
+                        <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
+                        <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
+                        <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
+                        <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
+                        <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
+                        <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
+                        <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
+                        <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
+                        <&topckgen CLK_TOP_ASM_M_SEL>,
+                        <&topckgen CLK_TOP_ASM_H_SEL>,
+                        <&topckgen CLK_TOP_UNIVPLL2_D4>,
+                        <&topckgen CLK_TOP_UNIVPLL2_D2>,
+                        <&topckgen CLK_TOP_SYSPLL_D5>;
+
+               clock-names = "infra_sys_audio_clk",
+                        "top_audio_mux1_sel",
+                        "top_audio_mux2_sel",
+                        "top_audio_mux1_div",
+                        "top_audio_mux2_div",
+                        "top_audio_48k_timing",
+                        "top_audio_44k_timing",
+                        "top_audpll_mux_sel",
+                        "top_apll_sel",
+                        "top_aud1_pll_98M",
+                        "top_aud2_pll_90M",
+                        "top_hadds2_pll_98M",
+                        "top_hadds2_pll_294M",
+                        "top_audpll",
+                        "top_audpll_d4",
+                        "top_audpll_d8",
+                        "top_audpll_d16",
+                        "top_audpll_d24",
+                        "top_audintbus_sel",
+                        "clk_26m",
+                        "top_syspll1_d4",
+                        "top_aud_k1_src_sel",
+                        "top_aud_k2_src_sel",
+                        "top_aud_k3_src_sel",
+                        "top_aud_k4_src_sel",
+                        "top_aud_k5_src_sel",
+                        "top_aud_k6_src_sel",
+                        "top_aud_k1_src_div",
+                        "top_aud_k2_src_div",
+                        "top_aud_k3_src_div",
+                        "top_aud_k4_src_div",
+                        "top_aud_k5_src_div",
+                        "top_aud_k6_src_div",
+                        "top_aud_i2s1_mclk",
+                        "top_aud_i2s2_mclk",
+                        "top_aud_i2s3_mclk",
+                        "top_aud_i2s4_mclk",
+                        "top_aud_i2s5_mclk",
+                        "top_aud_i2s6_mclk",
+                        "top_asm_m_sel",
+                        "top_asm_h_sel",
+                        "top_univpll2_d4",
+                        "top_univpll2_d2",
+                        "top_syspll_d5";
+       };
+
        mmc0: mmc@11230000 {
                compatible = "mediatek,mt7623-mmc",
                             "mediatek,mt8135-mmc";