ARM: dts: Add support for more than 2GB of memory for omap5

Some omap5 variants have more than 2GB of memory available as
optional models. Let's update the dts files to use two address
cells similar to what dra7 is using with commit dae320ec3173
("ARM: dts: DRA7: change address-cells and size-cells").

Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts
index c9390fa9c3621bca3a43484e96d3290f2e5d65a8..b153f604932a8856291d349227d0221d1210d57f 100644 (file)
--- a/arch/arm/boot/dts/omap5-cm-t54.dts
+++ b/arch/arm/boot/dts/omap5-cm-t54.dts
@@ -13,7 +13,7 @@ / {
 
        memory@80000000 {
                device_type = "memory";
-               reg = <0x80000000 0x7F000000>; /* 2048 MB */
+               reg = <0 0x80000000 0 0x7f000000>; /* 2048 MB */
        };
 
        aliases {

diff --git a/arch/arm/boot/dts/omap5-igep0050.dts b/arch/arm/boot/dts/omap5-igep0050.dts
index eceab970eba4870ca4ef06c5de6260f5e0ef0af7..44e03b9be1f1890901bc5f2eccc4aedc132784d6 100644 (file)
--- a/arch/arm/boot/dts/omap5-igep0050.dts
+++ b/arch/arm/boot/dts/omap5-igep0050.dts
@@ -16,7 +16,7 @@ / {
 
        memory@80000000 {
                device_type = "memory";
-               reg = <0x80000000 0x7f000000>; /* 2032 MB */
+               reg = <0x0 0x80000000 0 0x7f000000>;    /* 2032 MB */
        };
 
        gpio_keys {

diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
index 6966b77976ba8430be1f5317ac92ac4cf45d68d7..53d31a87b44bd7386c1b50333f130c4d8c9e0ec8 100644 (file)
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -15,7 +15,7 @@ / {
 
        memory@80000000 {
                device_type = "memory";
-               reg = <0x80000000 0x7F000000>; /* 2032 MB */
+               reg = <0 0x80000000 0 0x7f000000>; /* 2032 MB */
        };
 
        leds {

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index c2ef1285a3dd2f4c605693773d3c663257aca581..25262118ec3d042f01479daba0808b683d9976ff 100644 (file)
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -12,8 +12,8 @@
 #include <dt-bindings/pinctrl/omap.h>
 
 / {
-       #address-cells = <1>;
-       #size-cells = <1>;
+       #address-cells = <2>;
+       #size-cells = <2>;
 
        compatible = "ti,omap5";
        interrupt-parent = <&wakeupgen>;
@@ -90,10 +90,10 @@ gic: interrupt-controller@48211000 {
                compatible = "arm,cortex-a15-gic";
                interrupt-controller;
                #interrupt-cells = <3>;
-               reg = <0x48211000 0x1000>,
-                     <0x48212000 0x1000>,
-                     <0x48214000 0x2000>,
-                     <0x48216000 0x2000>;
+               reg = <0 0x48211000 0 0x1000>,
+                     <0 0x48212000 0 0x1000>,
+                     <0 0x48214000 0 0x2000>,
+                     <0 0x48216000 0 0x2000>;
                interrupt-parent = <&gic>;
        };
 
@@ -101,7 +101,7 @@ wakeupgen: interrupt-controller@48281000 {
                compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
                interrupt-controller;
                #interrupt-cells = <3>;
-               reg = <0x48281000 0x1000>;
+               reg = <0 0x48281000 0 0x1000>;
                interrupt-parent = <&gic>;
        };
 
@@ -129,11 +129,11 @@ ocp {
                compatible = "ti,omap5-l3-noc", "simple-bus";
                #address-cells = <1>;
                #size-cells = <1>;
-               ranges;
+               ranges = <0 0 0 0xc0000000>;
                ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
-               reg = <0x44000000 0x2000>,
-                     <0x44800000 0x3000>,
-                     <0x45000000 0x4000>;
+               reg = <0 0x44000000 0 0x2000>,
+                     <0 0x44800000 0 0x3000>,
+                     <0 0x45000000 0 0x4000>;
                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;