]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
net: hns3: Add support to enable and disable hw errors
authorShiju Jose <shiju.jose@huawei.com>
Fri, 19 Oct 2018 19:15:28 +0000 (20:15 +0100)
committerDavid S. Miller <davem@davemloft.net>
Tue, 23 Oct 2018 02:31:13 +0000 (19:31 -0700)
This patch adds functions to enable and disable hw errors.

Signed-off-by: Shiju Jose <shiju.jose@huawei.com>
Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

index 83aca6f8935526454ec6f84410bd895b1d765a59..d2640d14522224842d0ce5e3ce3477a09b3db3f8 100644 (file)
@@ -7,6 +7,28 @@ static const struct hclge_hw_blk hw_blk[] = {
        { /* sentinel */ }
 };
 
+int hclge_hw_error_set_state(struct hclge_dev *hdev, bool state)
+{
+       struct device *dev = &hdev->pdev->dev;
+       int ret = 0;
+       int i = 0;
+
+       while (hw_blk[i].name) {
+               if (!hw_blk[i].enable_error) {
+                       i++;
+                       continue;
+               }
+               ret = hw_blk[i].enable_error(hdev, state);
+               if (ret) {
+                       dev_err(dev, "fail(%d) to en/disable err int\n", ret);
+                       return ret;
+               }
+               i++;
+       }
+
+       return ret;
+}
+
 pci_ers_result_t hclge_process_ras_hw_error(struct hnae3_ae_dev *ae_dev)
 {
        struct hclge_dev *hdev = ae_dev->priv;
index ea1637cf63e1d98a87f2a0722b626901d2a6d95d..373e9bf2756695319a396600f3f9c3881226f23e 100644 (file)
@@ -21,9 +21,11 @@ enum hclge_err_int_type {
 struct hclge_hw_blk {
        u32 msk;
        const char *name;
+       int (*enable_error)(struct hclge_dev *hdev, bool en);
        void (*process_error)(struct hclge_dev *hdev,
                              enum hclge_err_int_type type);
 };
 
+int hclge_hw_error_set_state(struct hclge_dev *hdev, bool state);
 pci_ers_result_t hclge_process_ras_hw_error(struct hnae3_ae_dev *ae_dev);
 #endif
index 50753658b8d7327eaa5212aac5b1ead825a4aa74..082ea9749a54f875559b91dcf4f59e79b325f6c5 100644 (file)
@@ -6759,6 +6759,13 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
                goto err_mdiobus_unreg;
        }
 
+       ret = hclge_hw_error_set_state(hdev, true);
+       if (ret) {
+               dev_err(&pdev->dev,
+                       "hw error interrupts enable failed, ret =%d\n", ret);
+               goto err_mdiobus_unreg;
+       }
+
        hclge_dcb_ops_set(hdev);
 
        timer_setup(&hdev->service_timer, hclge_service_timer, 0);
@@ -6896,6 +6903,7 @@ static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
        hclge_enable_vector(&hdev->misc_vector, false);
        synchronize_irq(hdev->misc_vector.vector_irq);
 
+       hclge_hw_error_set_state(hdev, false);
        hclge_destroy_cmd_queue(&hdev->hw);
        hclge_misc_irq_uninit(hdev);
        hclge_pci_uninit(hdev);