drm/i915: Use cdclk_state->voltage on VLV/CHV

Store the punit DSPFREQUAR value into cdclk_state->voltage on
VLV/CHV. Since we can actually read that out from the hardware
this can give us a bit more cross checking between the hardware
and software state.

v2: Don't break waiting for cdclk change on VLV/CHV
v3: Split out the cdclk sanity check in vlv_set_cdclk() (Rodrigo)
v4: s/voltage/voltage_level/ (Rodrigo)

Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171024095216.1638-4-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 6dad2efd5e27640e75b0c89c631aacbe8b6cc24c..8bc0930825118b2502586f59da0394711a5d5470 100644 (file)
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -437,13 +437,45 @@ static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
                return 200000;
 }
 
+static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
+{
+       if (IS_VALLEYVIEW(dev_priv)) {
+               if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
+                       return 2;
+               else if (cdclk >= 266667)
+                       return 1;
+               else
+                       return 0;
+       } else {
+               /*
+                * Specs are full of misinformation, but testing on actual
+                * hardware has shown that we just need to write the desired
+                * CCK divider into the Punit register.
+                */
+               return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
+       }
+}
+
 static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
                          struct intel_cdclk_state *cdclk_state)
 {
+       u32 val;
+
        cdclk_state->vco = vlv_get_hpll_vco(dev_priv);
        cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
                                               CCK_DISPLAY_CLOCK_CONTROL,
                                               cdclk_state->vco);
+
+       mutex_lock(&dev_priv->pcu_lock);
+       val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
+       mutex_unlock(&dev_priv->pcu_lock);
+
+       if (IS_VALLEYVIEW(dev_priv))
+               cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK) >>
+                       DSPFREQGUAR_SHIFT;
+       else
+               cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
+                       DSPFREQGUAR_SHIFT_CHV;
 }
 
 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
@@ -486,7 +518,7 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
                          const struct intel_cdclk_state *cdclk_state)
 {
        int cdclk = cdclk_state->cdclk;
-       u32 val, cmd;
+       u32 val, cmd = cdclk_state->voltage_level;
 
        /* There are cases where we can end up here with power domains
         * off and a CDCLK frequency other than the minimum, like when
@@ -496,13 +528,6 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
         */
        intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
 
-       if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
-               cmd = 2;
-       else if (cdclk == 266667)
-               cmd = 1;
-       else
-               cmd = 0;
-
        mutex_lock(&dev_priv->pcu_lock);
        val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
        val &= ~DSPFREQGUAR_MASK;
@@ -562,7 +587,7 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
                          const struct intel_cdclk_state *cdclk_state)
 {
        int cdclk = cdclk_state->cdclk;
-       u32 val, cmd;
+       u32 val, cmd = cdclk_state->voltage_level;
 
        switch (cdclk) {
        case 333333:
@@ -583,13 +608,6 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
         */
        intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
 
-       /*
-        * Specs are full of misinformation, but testing on actual
-        * hardware has shown that we just need to write the desired
-        * CCK divider into the Punit register.
-        */
-       cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
-
        mutex_lock(&dev_priv->pcu_lock);
        val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
        val &= ~DSPFREQGUAR_MASK_CHV;
@@ -1859,11 +1877,15 @@ static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
        cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
 
        intel_state->cdclk.logical.cdclk = cdclk;
+       intel_state->cdclk.logical.voltage_level =
+               vlv_calc_voltage_level(dev_priv, cdclk);
 
        if (!intel_state->active_crtcs) {
                cdclk = vlv_calc_cdclk(dev_priv, 0);
 
                intel_state->cdclk.actual.cdclk = cdclk;
+               intel_state->cdclk.actual.voltage_level =
+                       vlv_calc_voltage_level(dev_priv, cdclk);
        } else {
                intel_state->cdclk.actual =
                        intel_state->cdclk.logical;