Merge remote-tracking branch 'airlied/drm-next' into drm-intel-next-queued

Backmerge request by Jani to get at

commit 249c4f538b1aae55d41699f8bafc6cb762a7f48f
Author: Deepak M <m.deepak@intel.com>
Date:   Wed Mar 30 17:03:39 2016 +0300

    drm: Add new DCS commands in the enum list

Some simple conflicts in intel_dp.c.

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>

diff --cc Documentation/DocBook/gpu.tmpl
Simple merge

diff --cc drivers/gpu/drm/Makefile
Simple merge

diff --cc drivers/gpu/drm/i915/i915_debugfs.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_drv.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_gem.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_display.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_dp.c
index ef8f8944d6993fbe9ff85f8201ca4fe5026e3d30,f192f58708c25dbedf74994b4a377098093f0dc3..36330026ceffa528b276b2b777f29e6dbe8de717
--- 1/drivers/gpu/drm/i915/intel_dp.c
--- 2/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@@ -2793,40 -3042,37 +2793,9 @@@ static void chv_dp_pre_pll_enable(struc
  
  static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
  {
 -      struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 -      enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
 -      u32 val;
 -
 -      mutex_lock(&dev_priv->sb_lock);
 -
 -      /* disable left/right clock distribution */
 -      if (pipe != PIPE_B) {
 -              val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
 -              val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
 -              vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
 -      } else {
 -              val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
 -              val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
 -              vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
 -      }
 -
 -      mutex_unlock(&dev_priv->sb_lock);
 -
 -      /*
 -       * Leave the power down bit cleared for at least one
 -       * lane so that chv_powergate_phy_ch() will power
 -       * on something when the channel is otherwise unused.
 -       * When the port is off and the override is removed
 -       * the lanes power down anyway, so otherwise it doesn't
 -       * really matter what the state of power down bits is
 -       * after this.
 -       */
 -      chv_phy_powergate_lanes(encoder, false, 0x0);
 +      chv_phy_post_pll_disable(encoder);
  }
  
- /*
-  * Native read with retry for link status and receiver capability reads for
-  * cases where the sink may still be asleep.
-  *
-  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
-  * supposed to retry 3 times per the spec.
-  */
- static ssize_t
- intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
-                       void *buffer, size_t size)
- {
-       ssize_t ret;
-       int i;
- 
-       /*
-        * Sometime we just get the same incorrect byte repeated
-        * over the entire buffer. Doing just one throw away read
-        * initially seems to "solve" it.
-        */
-       drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
- 
-       for (i = 0; i < 3; i++) {
-               ret = drm_dp_dpcd_read(aux, offset, buffer, size);
-               if (ret == size)
-                       return ret;
-               msleep(1);
-       }
- 
-       return ret;
- }
- 
  /*
   * Fetch AUX CH registers 0x202 - 0x207 which contain
   * link status information
@@@ -3365,9 -3714,10 +3332,9 @@@ intel_dp_get_dpcd(struct intel_dp *inte
        struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
        struct drm_device *dev = dig_port->base.base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
 -      uint8_t rev;
  
-       if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
-                                   sizeof(intel_dp->dpcd)) < 0)
+       if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
+                            sizeof(intel_dp->dpcd)) < 0)
                return false; /* aux transfer failed */
  
        DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
@@@ -3421,15 -3771,6 +3388,15 @@@
                        DRM_DEBUG_KMS("PSR2 %s on sink",
                                dev_priv->psr.psr2_support ? "supported" : "not supported");
                }
-                               (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV,
 +
 +              /* Read the eDP Display control capabilities registers */
 +              memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));
 +              if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
++                              (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
 +                                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
 +                                                              sizeof(intel_dp->edp_dpcd)))
 +                      DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
 +                                      intel_dp->edp_dpcd);
        }
  
        DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",

diff --cc drivers/gpu/drm/i915/intel_dp_mst.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_drv.h
Simple merge

diff --cc include/drm/drm_dp_helper.h
Simple merge