drm/amdgpu: rename amdgpu_program_register_sequence

add device for consistency with other functions in this file.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 81c1ddb9eb3a487bd24bfbf979620632c528d7e8..f10f4fc7dbe0fd77a5a2250cccb3d04c9cc37c30 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1913,7 +1913,7 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
 int amdgpu_ttm_init(struct amdgpu_device *adev);
 void amdgpu_ttm_fini(struct amdgpu_device *adev);
-void amdgpu_program_register_sequence(struct amdgpu_device *adev,
+void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
                                             const u32 *registers,
                                             const u32 array_size);
 

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7b44ca29a2c8ddd7c632ff9c670137ef6796811a..05e5c6822f9c1dd8fd77e07985fcbde0ce631075 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -342,7 +342,7 @@ static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
 }
 
 /**
- * amdgpu_program_register_sequence - program an array of registers.
+ * amdgpu_device_program_register_sequence - program an array of registers.
  *
  * @adev: amdgpu_device pointer
  * @registers: pointer to the register array
@@ -351,9 +351,9 @@ static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
  * Programs an array or registers with and and or masks.
  * This is a helper for setting golden registers.
  */
-void amdgpu_program_register_sequence(struct amdgpu_device *adev,
-                                     const u32 *registers,
-                                     const u32 array_size)
+void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
+                                            const u32 *registers,
+                                            const u32 array_size)
 {
        u32 tmp, reg, and_mask, or_mask;
        int i;

diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 8ba056a2a5da9ede328b0bc5541d0b745b445df6..39d49712f8c9dafc2b2a909d1366268b36670c5f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -755,74 +755,74 @@ static void cik_init_golden_registers(struct amdgpu_device *adev)
 
        switch (adev->asic_type) {
        case CHIP_BONAIRE:
-               amdgpu_program_register_sequence(adev,
-                                                bonaire_mgcg_cgcg_init,
-                                                ARRAY_SIZE(bonaire_mgcg_cgcg_init));
-               amdgpu_program_register_sequence(adev,
-                                                bonaire_golden_registers,
-                                                ARRAY_SIZE(bonaire_golden_registers));
-               amdgpu_program_register_sequence(adev,
-                                                bonaire_golden_common_registers,
-                                                ARRAY_SIZE(bonaire_golden_common_registers));
-               amdgpu_program_register_sequence(adev,
-                                                bonaire_golden_spm_registers,
-                                                ARRAY_SIZE(bonaire_golden_spm_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       bonaire_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(bonaire_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       bonaire_golden_registers,
+                                                       ARRAY_SIZE(bonaire_golden_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       bonaire_golden_common_registers,
+                                                       ARRAY_SIZE(bonaire_golden_common_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       bonaire_golden_spm_registers,
+                                                       ARRAY_SIZE(bonaire_golden_spm_registers));
                break;
        case CHIP_KABINI:
-               amdgpu_program_register_sequence(adev,
-                                                kalindi_mgcg_cgcg_init,
-                                                ARRAY_SIZE(kalindi_mgcg_cgcg_init));
-               amdgpu_program_register_sequence(adev,
-                                                kalindi_golden_registers,
-                                                ARRAY_SIZE(kalindi_golden_registers));
-               amdgpu_program_register_sequence(adev,
-                                                kalindi_golden_common_registers,
-                                                ARRAY_SIZE(kalindi_golden_common_registers));
-               amdgpu_program_register_sequence(adev,
-                                                kalindi_golden_spm_registers,
-                                                ARRAY_SIZE(kalindi_golden_spm_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       kalindi_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(kalindi_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       kalindi_golden_registers,
+                                                       ARRAY_SIZE(kalindi_golden_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       kalindi_golden_common_registers,
+                                                       ARRAY_SIZE(kalindi_golden_common_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       kalindi_golden_spm_registers,
+                                                       ARRAY_SIZE(kalindi_golden_spm_registers));
                break;
        case CHIP_MULLINS:
-               amdgpu_program_register_sequence(adev,
-                                                kalindi_mgcg_cgcg_init,
-                                                ARRAY_SIZE(kalindi_mgcg_cgcg_init));
-               amdgpu_program_register_sequence(adev,
-                                                godavari_golden_registers,
-                                                ARRAY_SIZE(godavari_golden_registers));
-               amdgpu_program_register_sequence(adev,
-                                                kalindi_golden_common_registers,
-                                                ARRAY_SIZE(kalindi_golden_common_registers));
-               amdgpu_program_register_sequence(adev,
-                                                kalindi_golden_spm_registers,
-                                                ARRAY_SIZE(kalindi_golden_spm_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       kalindi_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(kalindi_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       godavari_golden_registers,
+                                                       ARRAY_SIZE(godavari_golden_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       kalindi_golden_common_registers,
+                                                       ARRAY_SIZE(kalindi_golden_common_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       kalindi_golden_spm_registers,
+                                                       ARRAY_SIZE(kalindi_golden_spm_registers));
                break;
        case CHIP_KAVERI:
-               amdgpu_program_register_sequence(adev,
-                                                spectre_mgcg_cgcg_init,
-                                                ARRAY_SIZE(spectre_mgcg_cgcg_init));
-               amdgpu_program_register_sequence(adev,
-                                                spectre_golden_registers,
-                                                ARRAY_SIZE(spectre_golden_registers));
-               amdgpu_program_register_sequence(adev,
-                                                spectre_golden_common_registers,
-                                                ARRAY_SIZE(spectre_golden_common_registers));
-               amdgpu_program_register_sequence(adev,
-                                                spectre_golden_spm_registers,
-                                                ARRAY_SIZE(spectre_golden_spm_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       spectre_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(spectre_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       spectre_golden_registers,
+                                                       ARRAY_SIZE(spectre_golden_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       spectre_golden_common_registers,
+                                                       ARRAY_SIZE(spectre_golden_common_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       spectre_golden_spm_registers,
+                                                       ARRAY_SIZE(spectre_golden_spm_registers));
                break;
        case CHIP_HAWAII:
-               amdgpu_program_register_sequence(adev,
-                                                hawaii_mgcg_cgcg_init,
-                                                ARRAY_SIZE(hawaii_mgcg_cgcg_init));
-               amdgpu_program_register_sequence(adev,
-                                                hawaii_golden_registers,
-                                                ARRAY_SIZE(hawaii_golden_registers));
-               amdgpu_program_register_sequence(adev,
-                                                hawaii_golden_common_registers,
-                                                ARRAY_SIZE(hawaii_golden_common_registers));
-               amdgpu_program_register_sequence(adev,
-                                                hawaii_golden_spm_registers,
-                                                ARRAY_SIZE(hawaii_golden_spm_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       hawaii_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(hawaii_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       hawaii_golden_registers,
+                                                       ARRAY_SIZE(hawaii_golden_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       hawaii_golden_common_registers,
+                                                       ARRAY_SIZE(hawaii_golden_common_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       hawaii_golden_spm_registers,
+                                                       ARRAY_SIZE(hawaii_golden_spm_registers));
                break;
        default:
                break;

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index a397111c2cedb9d34aa2d4de292af9bbe19e3499..f34bc68aadfb119380e5f6ff1a279a996d4f453a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -145,20 +145,20 @@ static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
 {
        switch (adev->asic_type) {
        case CHIP_FIJI:
-               amdgpu_program_register_sequence(adev,
-                                                fiji_mgcg_cgcg_init,
-                                                ARRAY_SIZE(fiji_mgcg_cgcg_init));
-               amdgpu_program_register_sequence(adev,
-                                                golden_settings_fiji_a10,
-                                                ARRAY_SIZE(golden_settings_fiji_a10));
+               amdgpu_device_program_register_sequence(adev,
+                                                       fiji_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(fiji_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       golden_settings_fiji_a10,
+                                                       ARRAY_SIZE(golden_settings_fiji_a10));
                break;
        case CHIP_TONGA:
-               amdgpu_program_register_sequence(adev,
-                                                tonga_mgcg_cgcg_init,
-                                                ARRAY_SIZE(tonga_mgcg_cgcg_init));
-               amdgpu_program_register_sequence(adev,
-                                                golden_settings_tonga_a11,
-                                                ARRAY_SIZE(golden_settings_tonga_a11));
+               amdgpu_device_program_register_sequence(adev,
+                                                       tonga_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(tonga_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       golden_settings_tonga_a11,
+                                                       ARRAY_SIZE(golden_settings_tonga_a11));
                break;
        default:
                break;

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 67e670989e81539e9de3ceac09a4d2be99a22407..26378bd6aba45a86e18e1d7ac122182a7730a811 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -154,28 +154,28 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
 {
        switch (adev->asic_type) {
        case CHIP_CARRIZO:
-               amdgpu_program_register_sequence(adev,
-                                                cz_mgcg_cgcg_init,
-                                                ARRAY_SIZE(cz_mgcg_cgcg_init));
-               amdgpu_program_register_sequence(adev,
-                                                cz_golden_settings_a11,
-                                                ARRAY_SIZE(cz_golden_settings_a11));
+               amdgpu_device_program_register_sequence(adev,
+                                                       cz_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(cz_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       cz_golden_settings_a11,
+                                                       ARRAY_SIZE(cz_golden_settings_a11));
                break;
        case CHIP_STONEY:
-               amdgpu_program_register_sequence(adev,
-                                                stoney_golden_settings_a11,
-                                                ARRAY_SIZE(stoney_golden_settings_a11));
+               amdgpu_device_program_register_sequence(adev,
+                                                       stoney_golden_settings_a11,
+                                                       ARRAY_SIZE(stoney_golden_settings_a11));
                break;
        case CHIP_POLARIS11:
        case CHIP_POLARIS12:
-               amdgpu_program_register_sequence(adev,
-                                                polaris11_golden_settings_a11,
-                                                ARRAY_SIZE(polaris11_golden_settings_a11));
+               amdgpu_device_program_register_sequence(adev,
+                                                       polaris11_golden_settings_a11,
+                                                       ARRAY_SIZE(polaris11_golden_settings_a11));
                break;
        case CHIP_POLARIS10:
-               amdgpu_program_register_sequence(adev,
-                                                polaris10_golden_settings_a11,
-                                                ARRAY_SIZE(polaris10_golden_settings_a11));
+               amdgpu_device_program_register_sequence(adev,
+                                                       polaris10_golden_settings_a11,
+                                                       ARRAY_SIZE(polaris10_golden_settings_a11));
                break;
        default:
                break;

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index c7dc69031fb56db38d3ed373a6954b8ef7660b19..4a9c28cd144d30419724cf7d36671330b3ebffd2 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -679,55 +679,55 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
 {
        switch (adev->asic_type) {
        case CHIP_TOPAZ:
-               amdgpu_program_register_sequence(adev,
-                                                iceland_mgcg_cgcg_init,
-                                                ARRAY_SIZE(iceland_mgcg_cgcg_init));
-               amdgpu_program_register_sequence(adev,
-                                                golden_settings_iceland_a11,
-                                                ARRAY_SIZE(golden_settings_iceland_a11));
-               amdgpu_program_register_sequence(adev,
-                                                iceland_golden_common_all,
-                                                ARRAY_SIZE(iceland_golden_common_all));
+               amdgpu_device_program_register_sequence(adev,
+                                                       iceland_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(iceland_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       golden_settings_iceland_a11,
+                                                       ARRAY_SIZE(golden_settings_iceland_a11));
+               amdgpu_device_program_register_sequence(adev,
+                                                       iceland_golden_common_all,
+                                                       ARRAY_SIZE(iceland_golden_common_all));
                break;
        case CHIP_FIJI:
-               amdgpu_program_register_sequence(adev,
-                                                fiji_mgcg_cgcg_init,
-                                                ARRAY_SIZE(fiji_mgcg_cgcg_init));
-               amdgpu_program_register_sequence(adev,
-                                                golden_settings_fiji_a10,
-                                                ARRAY_SIZE(golden_settings_fiji_a10));
-               amdgpu_program_register_sequence(adev,
-                                                fiji_golden_common_all,
-                                                ARRAY_SIZE(fiji_golden_common_all));
+               amdgpu_device_program_register_sequence(adev,
+                                                       fiji_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(fiji_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       golden_settings_fiji_a10,
+                                                       ARRAY_SIZE(golden_settings_fiji_a10));
+               amdgpu_device_program_register_sequence(adev,
+                                                       fiji_golden_common_all,
+                                                       ARRAY_SIZE(fiji_golden_common_all));
                break;
 
        case CHIP_TONGA:
-               amdgpu_program_register_sequence(adev,
-                                                tonga_mgcg_cgcg_init,
-                                                ARRAY_SIZE(tonga_mgcg_cgcg_init));
-               amdgpu_program_register_sequence(adev,
-                                                golden_settings_tonga_a11,
-                                                ARRAY_SIZE(golden_settings_tonga_a11));
-               amdgpu_program_register_sequence(adev,
-                                                tonga_golden_common_all,
-                                                ARRAY_SIZE(tonga_golden_common_all));
+               amdgpu_device_program_register_sequence(adev,
+                                                       tonga_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(tonga_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       golden_settings_tonga_a11,
+                                                       ARRAY_SIZE(golden_settings_tonga_a11));
+               amdgpu_device_program_register_sequence(adev,
+                                                       tonga_golden_common_all,
+                                                       ARRAY_SIZE(tonga_golden_common_all));
                break;
        case CHIP_POLARIS11:
        case CHIP_POLARIS12:
-               amdgpu_program_register_sequence(adev,
-                                                golden_settings_polaris11_a11,
-                                                ARRAY_SIZE(golden_settings_polaris11_a11));
-               amdgpu_program_register_sequence(adev,
-                                                polaris11_golden_common_all,
-                                                ARRAY_SIZE(polaris11_golden_common_all));
+               amdgpu_device_program_register_sequence(adev,
+                                                       golden_settings_polaris11_a11,
+                                                       ARRAY_SIZE(golden_settings_polaris11_a11));
+               amdgpu_device_program_register_sequence(adev,
+                                                       polaris11_golden_common_all,
+                                                       ARRAY_SIZE(polaris11_golden_common_all));
                break;
        case CHIP_POLARIS10:
-               amdgpu_program_register_sequence(adev,
-                                                golden_settings_polaris10_a11,
-                                                ARRAY_SIZE(golden_settings_polaris10_a11));
-               amdgpu_program_register_sequence(adev,
-                                                polaris10_golden_common_all,
-                                                ARRAY_SIZE(polaris10_golden_common_all));
+               amdgpu_device_program_register_sequence(adev,
+                                                       golden_settings_polaris10_a11,
+                                                       ARRAY_SIZE(golden_settings_polaris10_a11));
+               amdgpu_device_program_register_sequence(adev,
+                                                       polaris10_golden_common_all,
+                                                       ARRAY_SIZE(polaris10_golden_common_all));
                WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C);
                if (adev->pdev->revision == 0xc7 &&
                    ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) ||
@@ -738,26 +738,26 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
                }
                break;
        case CHIP_CARRIZO:
-               amdgpu_program_register_sequence(adev,
-                                                cz_mgcg_cgcg_init,
-                                                ARRAY_SIZE(cz_mgcg_cgcg_init));
-               amdgpu_program_register_sequence(adev,
-                                                cz_golden_settings_a11,
-                                                ARRAY_SIZE(cz_golden_settings_a11));
-               amdgpu_program_register_sequence(adev,
-                                                cz_golden_common_all,
-                                                ARRAY_SIZE(cz_golden_common_all));
+               amdgpu_device_program_register_sequence(adev,
+                                                       cz_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(cz_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       cz_golden_settings_a11,
+                                                       ARRAY_SIZE(cz_golden_settings_a11));
+               amdgpu_device_program_register_sequence(adev,
+                                                       cz_golden_common_all,
+                                                       ARRAY_SIZE(cz_golden_common_all));
                break;
        case CHIP_STONEY:
-               amdgpu_program_register_sequence(adev,
-                                                stoney_mgcg_cgcg_init,
-                                                ARRAY_SIZE(stoney_mgcg_cgcg_init));
-               amdgpu_program_register_sequence(adev,
-                                                stoney_golden_settings_a11,
-                                                ARRAY_SIZE(stoney_golden_settings_a11));
-               amdgpu_program_register_sequence(adev,
-                                                stoney_golden_common_all,
-                                                ARRAY_SIZE(stoney_golden_common_all));
+               amdgpu_device_program_register_sequence(adev,
+                                                       stoney_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(stoney_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       stoney_golden_settings_a11,
+                                                       ARRAY_SIZE(stoney_golden_settings_a11));
+               amdgpu_device_program_register_sequence(adev,
+                                                       stoney_golden_common_all,
+                                                       ARRAY_SIZE(stoney_golden_common_all));
                break;
        default:
                break;

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 9c28e18741ea11a23fcf1402127bbe42d6b9bb71..c4285395b5fe2b987c7300720023f131d5b296a8 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -67,12 +67,12 @@ static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
 {
        switch (adev->asic_type) {
        case CHIP_TOPAZ:
-               amdgpu_program_register_sequence(adev,
-                                                iceland_mgcg_cgcg_init,
-                                                ARRAY_SIZE(iceland_mgcg_cgcg_init));
-               amdgpu_program_register_sequence(adev,
-                                                golden_settings_iceland_a11,
-                                                ARRAY_SIZE(golden_settings_iceland_a11));
+               amdgpu_device_program_register_sequence(adev,
+                                                       iceland_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(iceland_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       golden_settings_iceland_a11,
+                                                       ARRAY_SIZE(golden_settings_iceland_a11));
                break;
        default:
                break;

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index efed20ac4a016c0bbea0f7ded553170bad0210b2..6641276ecbdf1e1c53c2a969a931ddd4273192b0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -120,44 +120,44 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
 {
        switch (adev->asic_type) {
        case CHIP_FIJI:
-               amdgpu_program_register_sequence(adev,
-                                                fiji_mgcg_cgcg_init,
-                                                ARRAY_SIZE(fiji_mgcg_cgcg_init));
-               amdgpu_program_register_sequence(adev,
-                                                golden_settings_fiji_a10,
-                                                ARRAY_SIZE(golden_settings_fiji_a10));
+               amdgpu_device_program_register_sequence(adev,
+                                                       fiji_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(fiji_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       golden_settings_fiji_a10,
+                                                       ARRAY_SIZE(golden_settings_fiji_a10));
                break;
        case CHIP_TONGA:
-               amdgpu_program_register_sequence(adev,
-                                                tonga_mgcg_cgcg_init,
-                                                ARRAY_SIZE(tonga_mgcg_cgcg_init));
-               amdgpu_program_register_sequence(adev,
-                                                golden_settings_tonga_a11,
-                                                ARRAY_SIZE(golden_settings_tonga_a11));
+               amdgpu_device_program_register_sequence(adev,
+                                                       tonga_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(tonga_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       golden_settings_tonga_a11,
+                                                       ARRAY_SIZE(golden_settings_tonga_a11));
                break;
        case CHIP_POLARIS11:
        case CHIP_POLARIS12:
-               amdgpu_program_register_sequence(adev,
-                                                golden_settings_polaris11_a11,
-                                                ARRAY_SIZE(golden_settings_polaris11_a11));
+               amdgpu_device_program_register_sequence(adev,
+                                                       golden_settings_polaris11_a11,
+                                                       ARRAY_SIZE(golden_settings_polaris11_a11));
                break;
        case CHIP_POLARIS10:
-               amdgpu_program_register_sequence(adev,
-                                                golden_settings_polaris10_a11,
-                                                ARRAY_SIZE(golden_settings_polaris10_a11));
+               amdgpu_device_program_register_sequence(adev,
+                                                       golden_settings_polaris10_a11,
+                                                       ARRAY_SIZE(golden_settings_polaris10_a11));
                break;
        case CHIP_CARRIZO:
-               amdgpu_program_register_sequence(adev,
-                                                cz_mgcg_cgcg_init,
-                                                ARRAY_SIZE(cz_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       cz_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(cz_mgcg_cgcg_init));
                break;
        case CHIP_STONEY:
-               amdgpu_program_register_sequence(adev,
-                                                stoney_mgcg_cgcg_init,
-                                                ARRAY_SIZE(stoney_mgcg_cgcg_init));
-               amdgpu_program_register_sequence(adev,
-                                                golden_settings_stoney_common,
-                                                ARRAY_SIZE(golden_settings_stoney_common));
+               amdgpu_device_program_register_sequence(adev,
+                                                       stoney_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(stoney_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       golden_settings_stoney_common,
+                                                       ARRAY_SIZE(golden_settings_stoney_common));
                break;
        default:
                break;

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 5da2272bd3132b5b9989c118b2681f7295b4e048..899ffe50cb50069f77ac69243324625642d12602 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -918,9 +918,9 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
        bool value;
        u32 tmp;
 
-       amdgpu_program_register_sequence(adev,
-               golden_settings_vega10_hdp,
-               ARRAY_SIZE(golden_settings_vega10_hdp));
+       amdgpu_device_program_register_sequence(adev,
+                                               golden_settings_vega10_hdp,
+                                               ARRAY_SIZE(golden_settings_vega10_hdp));
 
        if (adev->gart.robj == NULL) {
                dev_err(adev->dev, "No VRAM object for PCIE GART.\n");

diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
index da7c261d5d876b66ce37be78d954003ea27ee1a2..af2d47e9abdc131197b8cb792d348f48bb0a56cd 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
@@ -279,32 +279,32 @@ void xgpu_vi_init_golden_registers(struct amdgpu_device *adev)
 {
        switch (adev->asic_type) {
        case CHIP_FIJI:
-               amdgpu_program_register_sequence(adev,
-                                                xgpu_fiji_mgcg_cgcg_init,
-                                                ARRAY_SIZE(
-                                                xgpu_fiji_mgcg_cgcg_init));
-               amdgpu_program_register_sequence(adev,
-                                                xgpu_fiji_golden_settings_a10,
-                                                ARRAY_SIZE(
-                                                xgpu_fiji_golden_settings_a10));
-               amdgpu_program_register_sequence(adev,
-                                                xgpu_fiji_golden_common_all,
-                                                ARRAY_SIZE(
-                                                xgpu_fiji_golden_common_all));
+               amdgpu_device_program_register_sequence(adev,
+                                                       xgpu_fiji_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(
+                                                               xgpu_fiji_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       xgpu_fiji_golden_settings_a10,
+                                                       ARRAY_SIZE(
+                                                               xgpu_fiji_golden_settings_a10));
+               amdgpu_device_program_register_sequence(adev,
+                                                       xgpu_fiji_golden_common_all,
+                                                       ARRAY_SIZE(
+                                                               xgpu_fiji_golden_common_all));
                break;
        case CHIP_TONGA:
-               amdgpu_program_register_sequence(adev,
-                                                xgpu_tonga_mgcg_cgcg_init,
-                                                ARRAY_SIZE(
-                                                xgpu_tonga_mgcg_cgcg_init));
-               amdgpu_program_register_sequence(adev,
-                                                xgpu_tonga_golden_settings_a11,
-                                                ARRAY_SIZE(
-                                                xgpu_tonga_golden_settings_a11));
-               amdgpu_program_register_sequence(adev,
-                                                xgpu_tonga_golden_common_all,
-                                                ARRAY_SIZE(
-                                                xgpu_tonga_golden_common_all));
+               amdgpu_device_program_register_sequence(adev,
+                                                       xgpu_tonga_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(
+                                                               xgpu_tonga_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       xgpu_tonga_golden_settings_a11,
+                                                       ARRAY_SIZE(
+                                                               xgpu_tonga_golden_settings_a11));
+               amdgpu_device_program_register_sequence(adev,
+                                                       xgpu_tonga_golden_common_all,
+                                                       ARRAY_SIZE(
+                                                               xgpu_tonga_golden_common_all));
                break;
        default:
                BUG_ON("Doesn't support chip type.\n");

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 0c5b91a40f2267405dc306eda73b09f7af426b35..401552bae7f5be35dfe0dca5e464c09387883d42 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -93,12 +93,12 @@ static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
 {
        switch (adev->asic_type) {
        case CHIP_TOPAZ:
-               amdgpu_program_register_sequence(adev,
-                                                iceland_mgcg_cgcg_init,
-                                                ARRAY_SIZE(iceland_mgcg_cgcg_init));
-               amdgpu_program_register_sequence(adev,
-                                                golden_settings_iceland_a11,
-                                                ARRAY_SIZE(golden_settings_iceland_a11));
+               amdgpu_device_program_register_sequence(adev,
+                                                       iceland_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(iceland_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       golden_settings_iceland_a11,
+                                                       ARRAY_SIZE(golden_settings_iceland_a11));
                break;
        default:
                break;

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 4e031a2aad9d59980f9600eb9b7d1987e1366ee7..0735d4d0e56af6f18f85ef3dc8f848491bd117c9 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -192,47 +192,47 @@ static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
 {
        switch (adev->asic_type) {
        case CHIP_FIJI:
-               amdgpu_program_register_sequence(adev,
-                                                fiji_mgcg_cgcg_init,
-                                                ARRAY_SIZE(fiji_mgcg_cgcg_init));
-               amdgpu_program_register_sequence(adev,
-                                                golden_settings_fiji_a10,
-                                                ARRAY_SIZE(golden_settings_fiji_a10));
+               amdgpu_device_program_register_sequence(adev,
+                                                       fiji_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(fiji_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       golden_settings_fiji_a10,
+                                                       ARRAY_SIZE(golden_settings_fiji_a10));
                break;
        case CHIP_TONGA:
-               amdgpu_program_register_sequence(adev,
-                                                tonga_mgcg_cgcg_init,
-                                                ARRAY_SIZE(tonga_mgcg_cgcg_init));
-               amdgpu_program_register_sequence(adev,
-                                                golden_settings_tonga_a11,
-                                                ARRAY_SIZE(golden_settings_tonga_a11));
+               amdgpu_device_program_register_sequence(adev,
+                                                       tonga_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(tonga_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       golden_settings_tonga_a11,
+                                                       ARRAY_SIZE(golden_settings_tonga_a11));
                break;
        case CHIP_POLARIS11:
        case CHIP_POLARIS12:
-               amdgpu_program_register_sequence(adev,
-                                                golden_settings_polaris11_a11,
-                                                ARRAY_SIZE(golden_settings_polaris11_a11));
+               amdgpu_device_program_register_sequence(adev,
+                                                       golden_settings_polaris11_a11,
+                                                       ARRAY_SIZE(golden_settings_polaris11_a11));
                break;
        case CHIP_POLARIS10:
-               amdgpu_program_register_sequence(adev,
-                                                golden_settings_polaris10_a11,
-                                                ARRAY_SIZE(golden_settings_polaris10_a11));
+               amdgpu_device_program_register_sequence(adev,
+                                                       golden_settings_polaris10_a11,
+                                                       ARRAY_SIZE(golden_settings_polaris10_a11));
                break;
        case CHIP_CARRIZO:
-               amdgpu_program_register_sequence(adev,
-                                                cz_mgcg_cgcg_init,
-                                                ARRAY_SIZE(cz_mgcg_cgcg_init));
-               amdgpu_program_register_sequence(adev,
-                                                cz_golden_settings_a11,
-                                                ARRAY_SIZE(cz_golden_settings_a11));
+               amdgpu_device_program_register_sequence(adev,
+                                                       cz_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(cz_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       cz_golden_settings_a11,
+                                                       ARRAY_SIZE(cz_golden_settings_a11));
                break;
        case CHIP_STONEY:
-               amdgpu_program_register_sequence(adev,
-                                                stoney_mgcg_cgcg_init,
-                                                ARRAY_SIZE(stoney_mgcg_cgcg_init));
-               amdgpu_program_register_sequence(adev,
-                                                stoney_golden_settings_a11,
-                                                ARRAY_SIZE(stoney_golden_settings_a11));
+               amdgpu_device_program_register_sequence(adev,
+                                                       stoney_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(stoney_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       stoney_golden_settings_a11,
+                                                       ARRAY_SIZE(stoney_golden_settings_a11));
                break;
        default:
                break;

diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 49eef3090f085013e51ba6fcafcf75cb7ee0eecc..78baddb5d3001877f0d355573b82b58cf1eaca08 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1390,65 +1390,65 @@ static void si_init_golden_registers(struct amdgpu_device *adev)
 {
        switch (adev->asic_type) {
        case CHIP_TAHITI:
-               amdgpu_program_register_sequence(adev,
-                                                tahiti_golden_registers,
-                                                ARRAY_SIZE(tahiti_golden_registers));
-               amdgpu_program_register_sequence(adev,
-                                                tahiti_golden_rlc_registers,
-                                                ARRAY_SIZE(tahiti_golden_rlc_registers));
-               amdgpu_program_register_sequence(adev,
-                                                tahiti_mgcg_cgcg_init,
-                                                ARRAY_SIZE(tahiti_mgcg_cgcg_init));
-               amdgpu_program_register_sequence(adev,
-                                                tahiti_golden_registers2,
-                                                ARRAY_SIZE(tahiti_golden_registers2));
+               amdgpu_device_program_register_sequence(adev,
+                                                       tahiti_golden_registers,
+                                                       ARRAY_SIZE(tahiti_golden_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       tahiti_golden_rlc_registers,
+                                                       ARRAY_SIZE(tahiti_golden_rlc_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       tahiti_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(tahiti_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       tahiti_golden_registers2,
+                                                       ARRAY_SIZE(tahiti_golden_registers2));
                break;
        case CHIP_PITCAIRN:
-               amdgpu_program_register_sequence(adev,
-                                                pitcairn_golden_registers,
-                                                ARRAY_SIZE(pitcairn_golden_registers));
-               amdgpu_program_register_sequence(adev,
-                                                pitcairn_golden_rlc_registers,
-                                                ARRAY_SIZE(pitcairn_golden_rlc_registers));
-               amdgpu_program_register_sequence(adev,
-                                                pitcairn_mgcg_cgcg_init,
-                                                ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       pitcairn_golden_registers,
+                                                       ARRAY_SIZE(pitcairn_golden_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       pitcairn_golden_rlc_registers,
+                                                       ARRAY_SIZE(pitcairn_golden_rlc_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       pitcairn_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
                break;
        case CHIP_VERDE:
-               amdgpu_program_register_sequence(adev,
-                                                verde_golden_registers,
-                                                ARRAY_SIZE(verde_golden_registers));
-               amdgpu_program_register_sequence(adev,
-                                                verde_golden_rlc_registers,
-                                                ARRAY_SIZE(verde_golden_rlc_registers));
-               amdgpu_program_register_sequence(adev,
-                                                verde_mgcg_cgcg_init,
-                                                ARRAY_SIZE(verde_mgcg_cgcg_init));
-               amdgpu_program_register_sequence(adev,
-                                                verde_pg_init,
-                                                ARRAY_SIZE(verde_pg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       verde_golden_registers,
+                                                       ARRAY_SIZE(verde_golden_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       verde_golden_rlc_registers,
+                                                       ARRAY_SIZE(verde_golden_rlc_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       verde_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(verde_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       verde_pg_init,
+                                                       ARRAY_SIZE(verde_pg_init));
                break;
        case CHIP_OLAND:
-               amdgpu_program_register_sequence(adev,
-                                                oland_golden_registers,
-                                                ARRAY_SIZE(oland_golden_registers));
-               amdgpu_program_register_sequence(adev,
-                                                oland_golden_rlc_registers,
-                                                ARRAY_SIZE(oland_golden_rlc_registers));
-               amdgpu_program_register_sequence(adev,
-                                                oland_mgcg_cgcg_init,
-                                                ARRAY_SIZE(oland_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       oland_golden_registers,
+                                                       ARRAY_SIZE(oland_golden_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       oland_golden_rlc_registers,
+                                                       ARRAY_SIZE(oland_golden_rlc_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       oland_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(oland_mgcg_cgcg_init));
                break;
        case CHIP_HAINAN:
-               amdgpu_program_register_sequence(adev,
-                                                hainan_golden_registers,
-                                                ARRAY_SIZE(hainan_golden_registers));
-               amdgpu_program_register_sequence(adev,
-                                                hainan_golden_registers2,
-                                                ARRAY_SIZE(hainan_golden_registers2));
-               amdgpu_program_register_sequence(adev,
-                                                hainan_mgcg_cgcg_init,
-                                                ARRAY_SIZE(hainan_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       hainan_golden_registers,
+                                                       ARRAY_SIZE(hainan_golden_registers));
+               amdgpu_device_program_register_sequence(adev,
+                                                       hainan_golden_registers2,
+                                                       ARRAY_SIZE(hainan_golden_registers2));
+               amdgpu_device_program_register_sequence(adev,
+                                                       hainan_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(hainan_mgcg_cgcg_init));
                break;
 
 

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index bb8ca9489546aed8be038d8c67dd86b388289cd0..0b57c5d24510a1c5655b9b52c393e74fac76c984 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -282,29 +282,29 @@ static void vi_init_golden_registers(struct amdgpu_device *adev)
 
        switch (adev->asic_type) {
        case CHIP_TOPAZ:
-               amdgpu_program_register_sequence(adev,
-                                                iceland_mgcg_cgcg_init,
-                                                ARRAY_SIZE(iceland_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       iceland_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(iceland_mgcg_cgcg_init));
                break;
        case CHIP_FIJI:
-               amdgpu_program_register_sequence(adev,
-                                                fiji_mgcg_cgcg_init,
-                                                ARRAY_SIZE(fiji_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       fiji_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(fiji_mgcg_cgcg_init));
                break;
        case CHIP_TONGA:
-               amdgpu_program_register_sequence(adev,
-                                                tonga_mgcg_cgcg_init,
-                                                ARRAY_SIZE(tonga_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       tonga_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(tonga_mgcg_cgcg_init));
                break;
        case CHIP_CARRIZO:
-               amdgpu_program_register_sequence(adev,
-                                                cz_mgcg_cgcg_init,
-                                                ARRAY_SIZE(cz_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       cz_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(cz_mgcg_cgcg_init));
                break;
        case CHIP_STONEY:
-               amdgpu_program_register_sequence(adev,
-                                                stoney_mgcg_cgcg_init,
-                                                ARRAY_SIZE(stoney_mgcg_cgcg_init));
+               amdgpu_device_program_register_sequence(adev,
+                                                       stoney_mgcg_cgcg_init,
+                                                       ARRAY_SIZE(stoney_mgcg_cgcg_init));
                break;
        case CHIP_POLARIS11:
        case CHIP_POLARIS10: