clk: qcom: gcc-qcs404: Add cfg_offset for blsp1_uart3 clock

The CFG/M/N/D registers are at an offset of 0x20 from the CMD register
only for blsp1_uart3 clock, so add it for uart3 only.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Anu Ramanathan <anur@codeaurora.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index 64da032bb9edb35d571f013ca37582179493961c..493e055299b48fa5f0ca1aee2bc5f14af474a805 100644 (file)
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -678,6 +678,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
        .cmd_rcgr = 0x4014,
        .mnd_width = 16,
        .hid_width = 5,
+       .cfg_off = 0x20,
        .parent_map = gcc_parent_map_0,
        .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
        .clkr.hw.init = &(struct clk_init_data){