]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
clk: qcom: Add support to initialize alpha plls
authorRajendra Nayak <rnayak@codeaurora.org>
Thu, 29 Sep 2016 08:35:43 +0000 (14:05 +0530)
committerStephen Boyd <sboyd@codeaurora.org>
Wed, 2 Nov 2016 01:39:16 +0000 (18:39 -0700)
Add a function to do initial configuration of the alpha plls

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/qcom/clk-alpha-pll.c
drivers/clk/qcom/clk-alpha-pll.h

index 0cfbb2940e3e393dc81fbb1a4a881c135627ebac..a1188c86eea5c939e71c8ec152d86265036dbcf8 100644 (file)
@@ -49,6 +49,7 @@
 #define PLL_USER_CTL_U         0x14
 
 #define PLL_CONFIG_CTL         0x18
+#define PLL_CONFIG_CTL_U       0x20
 #define PLL_TEST_CTL           0x1c
 #define PLL_TEST_CTL_U         0x20
 #define PLL_STATUS             0x24
@@ -106,6 +107,36 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
 #define wait_for_pll_offline(pll) \
        wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
 
+void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
+                            const struct alpha_pll_config *config)
+{
+       u32 val, mask;
+       u32 off = pll->offset;
+
+       regmap_write(regmap, off + PLL_L_VAL, config->l);
+       regmap_write(regmap, off + PLL_ALPHA_VAL, config->alpha);
+       regmap_write(regmap, off + PLL_CONFIG_CTL, config->config_ctl_val);
+       regmap_write(regmap, off + PLL_CONFIG_CTL_U, config->config_ctl_hi_val);
+
+       val = config->main_output_mask;
+       val |= config->aux_output_mask;
+       val |= config->aux2_output_mask;
+       val |= config->early_output_mask;
+       val |= config->pre_div_val;
+       val |= config->post_div_val;
+       val |= config->vco_val;
+
+       mask = config->main_output_mask;
+       mask |= config->aux_output_mask;
+       mask |= config->aux2_output_mask;
+       mask |= config->early_output_mask;
+       mask |= config->pre_div_mask;
+       mask |= config->post_div_mask;
+       mask |= config->vco_mask;
+
+       regmap_update_bits(regmap, off + PLL_USER_CTL, mask, val);
+}
+
 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
 {
        int ret;
index 0deb286da7e3f1e1c1f08ef45c32b3f707576f5e..2f48530ec102fb2b40f821103144b99ead6dce41 100644 (file)
@@ -53,8 +53,28 @@ struct clk_alpha_pll_postdiv {
        struct clk_regmap clkr;
 };
 
+struct alpha_pll_config {
+       u32 l;
+       u32 alpha;
+       u32 config_ctl_val;
+       u32 config_ctl_hi_val;
+       u32 main_output_mask;
+       u32 aux_output_mask;
+       u32 aux2_output_mask;
+       u32 early_output_mask;
+       u32 pre_div_val;
+       u32 pre_div_mask;
+       u32 post_div_val;
+       u32 post_div_mask;
+       u32 vco_val;
+       u32 vco_mask;
+};
+
 extern const struct clk_ops clk_alpha_pll_ops;
 extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
 extern const struct clk_ops clk_alpha_pll_postdiv_ops;
 
+void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
+                            const struct alpha_pll_config *config);
+
 #endif