drm/i915: Extract the GuC interrupt handlers

Pull the GuC interrupt handlers out of i915_irq.c. They now use the GT
interrupt facilities rather than the central dispatch.

Based on a patch by Chris Wilson.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191024211642.7688-2-chris@chris-wilson.co.uk

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 37f7bcbf7dac8f44631016d9bf6f90b9350225ff..f129591821821fe8fff71831631a12b70b057a85 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -4,6 +4,8 @@
  */
 
 #include "gt/intel_gt.h"
+#include "gt/intel_gt_irq.h"
+#include "gt/intel_gt_pm_irq.h"
 #include "intel_guc.h"
 #include "intel_guc_ads.h"
 #include "intel_guc_submission.h"
@@ -77,6 +79,93 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
        guc->send_regs.fw_domains = fw_domains;
 }
 
+static void gen9_reset_guc_interrupts(struct intel_guc *guc)
+{
+       struct intel_gt *gt = guc_to_gt(guc);
+
+       assert_rpm_wakelock_held(&gt->i915->runtime_pm);
+
+       spin_lock_irq(&gt->irq_lock);
+       gen6_gt_pm_reset_iir(gt, gt->pm_guc_events);
+       spin_unlock_irq(&gt->irq_lock);
+}
+
+static void gen9_enable_guc_interrupts(struct intel_guc *guc)
+{
+       struct intel_gt *gt = guc_to_gt(guc);
+
+       assert_rpm_wakelock_held(&gt->i915->runtime_pm);
+
+       spin_lock_irq(&gt->irq_lock);
+       if (!guc->interrupts.enabled) {
+               WARN_ON_ONCE(intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
+                            gt->pm_guc_events);
+               guc->interrupts.enabled = true;
+               gen6_gt_pm_enable_irq(gt, gt->pm_guc_events);
+       }
+       spin_unlock_irq(&gt->irq_lock);
+}
+
+static void gen9_disable_guc_interrupts(struct intel_guc *guc)
+{
+       struct intel_gt *gt = guc_to_gt(guc);
+
+       assert_rpm_wakelock_held(&gt->i915->runtime_pm);
+
+       spin_lock_irq(&gt->irq_lock);
+       guc->interrupts.enabled = false;
+
+       gen6_gt_pm_disable_irq(gt, gt->pm_guc_events);
+
+       spin_unlock_irq(&gt->irq_lock);
+       intel_synchronize_irq(gt->i915);
+
+       gen9_reset_guc_interrupts(guc);
+}
+
+static void gen11_reset_guc_interrupts(struct intel_guc *guc)
+{
+       struct intel_gt *gt = guc_to_gt(guc);
+
+       spin_lock_irq(&gt->irq_lock);
+       gen11_gt_reset_one_iir(gt, 0, GEN11_GUC);
+       spin_unlock_irq(&gt->irq_lock);
+}
+
+static void gen11_enable_guc_interrupts(struct intel_guc *guc)
+{
+       struct intel_gt *gt = guc_to_gt(guc);
+
+       spin_lock_irq(&gt->irq_lock);
+       if (!guc->interrupts.enabled) {
+               u32 events = REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST);
+
+               WARN_ON_ONCE(gen11_gt_reset_one_iir(gt, 0, GEN11_GUC));
+               intel_uncore_write(gt->uncore,
+                                  GEN11_GUC_SG_INTR_ENABLE, events);
+               intel_uncore_write(gt->uncore,
+                                  GEN11_GUC_SG_INTR_MASK, ~events);
+               guc->interrupts.enabled = true;
+       }
+       spin_unlock_irq(&gt->irq_lock);
+}
+
+static void gen11_disable_guc_interrupts(struct intel_guc *guc)
+{
+       struct intel_gt *gt = guc_to_gt(guc);
+
+       spin_lock_irq(&gt->irq_lock);
+       guc->interrupts.enabled = false;
+
+       intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_MASK, ~0);
+       intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
+
+       spin_unlock_irq(&gt->irq_lock);
+       intel_synchronize_irq(gt->i915);
+
+       gen11_reset_guc_interrupts(guc);
+}
+
 void intel_guc_init_early(struct intel_guc *guc)
 {
        struct drm_i915_private *i915 = guc_to_gt(guc)->i915;

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 8a3aed17c3b74c6702e0ba0a23881f4f6247c4b7..0a3861c873ee037f37235f63898551277a5c8ff1 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -321,99 +321,6 @@ void ilk_update_display_irq(struct drm_i915_private *dev_priv,
        }
 }
 
-static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
-{
-       WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11);
-
-       return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
-}
-
-void gen9_reset_guc_interrupts(struct intel_guc *guc)
-{
-       struct intel_gt *gt = guc_to_gt(guc);
-
-       assert_rpm_wakelock_held(gt->uncore->rpm);
-
-       spin_lock_irq(&gt->irq_lock);
-       gen6_gt_pm_reset_iir(gt, gt->pm_guc_events);
-       spin_unlock_irq(&gt->irq_lock);
-}
-
-void gen9_enable_guc_interrupts(struct intel_guc *guc)
-{
-       struct intel_gt *gt = guc_to_gt(guc);
-
-       assert_rpm_wakelock_held(gt->uncore->rpm);
-
-       spin_lock_irq(&gt->irq_lock);
-       if (!guc->interrupts.enabled) {
-               WARN_ON_ONCE(intel_uncore_read(gt->uncore,
-                                              gen6_pm_iir(gt->i915)) &
-                            gt->pm_guc_events);
-               guc->interrupts.enabled = true;
-               gen6_gt_pm_enable_irq(gt, gt->pm_guc_events);
-       }
-       spin_unlock_irq(&gt->irq_lock);
-}
-
-void gen9_disable_guc_interrupts(struct intel_guc *guc)
-{
-       struct intel_gt *gt = guc_to_gt(guc);
-
-       assert_rpm_wakelock_held(gt->uncore->rpm);
-
-       spin_lock_irq(&gt->irq_lock);
-       guc->interrupts.enabled = false;
-
-       gen6_gt_pm_disable_irq(gt, gt->pm_guc_events);
-
-       spin_unlock_irq(&gt->irq_lock);
-       intel_synchronize_irq(gt->i915);
-
-       gen9_reset_guc_interrupts(guc);
-}
-
-void gen11_reset_guc_interrupts(struct intel_guc *guc)
-{
-       struct intel_gt *gt = guc_to_gt(guc);
-
-       spin_lock_irq(&gt->irq_lock);
-       gen11_gt_reset_one_iir(gt, 0, GEN11_GUC);
-       spin_unlock_irq(&gt->irq_lock);
-}
-
-void gen11_enable_guc_interrupts(struct intel_guc *guc)
-{
-       struct intel_gt *gt = guc_to_gt(guc);
-
-       spin_lock_irq(&gt->irq_lock);
-       if (!guc->interrupts.enabled) {
-               u32 events = REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST);
-
-               WARN_ON_ONCE(gen11_gt_reset_one_iir(gt, 0, GEN11_GUC));
-               intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_ENABLE, events);
-               intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_MASK, ~events);
-               guc->interrupts.enabled = true;
-       }
-       spin_unlock_irq(&gt->irq_lock);
-}
-
-void gen11_disable_guc_interrupts(struct intel_guc *guc)
-{
-       struct intel_gt *gt = guc_to_gt(guc);
-
-       spin_lock_irq(&gt->irq_lock);
-       guc->interrupts.enabled = false;
-
-       intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_MASK, ~0);
-       intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
-
-       spin_unlock_irq(&gt->irq_lock);
-       intel_synchronize_irq(gt->i915);
-
-       gen11_reset_guc_interrupts(guc);
-}
-
 /**
  * bdw_update_port_irq - update DE port interrupt
  * @dev_priv: driver private

diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
index d0d91c6e00d7a5f29568f0e8e19db2bef473bf40..812c47a9c2d6b87ada7e04c13f33e0666c440152 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.h
+++ b/drivers/gpu/drm/i915/i915_irq.h
@@ -17,9 +17,6 @@ struct drm_device;
 struct drm_display_mode;
 struct drm_i915_private;
 struct intel_crtc;
-struct intel_crtc;
-struct intel_gt;
-struct intel_guc;
 struct intel_uncore;
 
 void intel_irq_init(struct drm_i915_private *dev_priv);
@@ -103,12 +100,6 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
                                     u8 pipe_mask);
 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
                                     u8 pipe_mask);
-void gen9_reset_guc_interrupts(struct intel_guc *guc);
-void gen9_enable_guc_interrupts(struct intel_guc *guc);
-void gen9_disable_guc_interrupts(struct intel_guc *guc);
-void gen11_reset_guc_interrupts(struct intel_guc *guc);
-void gen11_enable_guc_interrupts(struct intel_guc *guc);
-void gen11_disable_guc_interrupts(struct intel_guc *guc);
 
 bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
                              bool in_vblank_irq, int *vpos, int *hpos,