drm/amd/pp: Fix bug that dpm level was not really locked

Lock the dpm levels when we use SW method to modify
the dpm tables directly to avoid a possible race
with the smu.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 0202841ae639cb3f406b3491b7d807e509b193b5..1d988ef1978e5ceb954a818cea6bbbac956b7f77 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -4650,20 +4650,26 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr,
        if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_AUTO)
                return -EINVAL;
 
-       tmp_result = smu7_freeze_sclk_mclk_dpm(hwmgr);
-       PP_ASSERT_WITH_CODE(!tmp_result,
-                       "Failed to freeze SCLK MCLK DPM!",
-                       result = tmp_result);
+       if (smum_is_dpm_running(hwmgr)) {
+               if (!data->sclk_dpm_key_disabled)
+                       smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_FreezeLevel);
+
+               if (!data->mclk_dpm_key_disabled)
+                       smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_FreezeLevel);
+       }
 
        tmp_result = smum_populate_requested_graphic_levels(hwmgr, request);
        PP_ASSERT_WITH_CODE(!tmp_result,
                        "Failed to populate requested graphic levels!",
                        result = tmp_result);
 
-       tmp_result = smu7_unfreeze_sclk_mclk_dpm(hwmgr);
-       PP_ASSERT_WITH_CODE(!tmp_result,
-                       "Failed to unfreeze SCLK MCLK DPM!",
-                       result = tmp_result);
+       if (smum_is_dpm_running(hwmgr)) {
+               if (!data->sclk_dpm_key_disabled)
+                       smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
+
+               if (!data->mclk_dpm_key_disabled)
+                       smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
+       }
 
        smu7_find_min_clock_masks(hwmgr, &sclk_mask, &mclk_mask,
                        request->min_sclk, request->min_mclk);