ARM: dts: r8a7792: Remove unit-address and reg from integrated cache

The Cortex-A15 cache controller is an integrated controller, and thus
the device node representing it should not have a unit-addresses or reg
property.

Fixes: 7c4163aae3d8e5b9 ("ARM: dts: r8a7792: initial SoC device tree")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index 8ecfda7a004ecb322b63e1fa0c8b3d1aa6851ca9..c762f44f7732f352d31d2ee4ad3c62616dc22e5b 100644 (file)
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -60,9 +60,8 @@ cpu1: cpu@1 {
                        next-level-cache = <&L2_CA15>;
                };
 
-               L2_CA15: cache-controller@0 {
+               L2_CA15: cache-controller-0 {
                        compatible = "cache";
-                       reg = <0>;
                        cache-unified;
                        cache-level = <2>;
                        power-domains = <&sysc R8A7792_PD_CA15_SCU>;