arm64: dts: qcom: msm8998: Add anoc2 smmu node

While there are several peripherals on the anoc2, most are not behind the
smmu.  However, the SoC integrated wlan block is behind the smmu, so we'll
need to control the smmu inorder to enable wifi.

Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Link: https://lore.kernel.org/r/20191107043313.4055-2-jeffrey.l.hugo@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index fc7838ea9a01023b0d4f43e765dde08adfba975b..d5263e4f64ce8ef163020d0a9b1c9932b557104b 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -847,6 +847,25 @@ anoc1_smmu: iommu@1680000 {
                                <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
                };
 
+               anoc2_smmu: iommu@16c0000 {
+                       compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
+                       reg = <0x016c0000 0x40000>;
+                       #iommu-cells = <1>;
+
+                       #global-interrupts = <0>;
+                       interrupts =
+                               <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
+                               <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
+                               <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
+                               <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
+                               <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
+                               <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
+                               <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>,
+                               <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
+                               <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+                               <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
+               };
+
                pcie0: pci@1c00000 {
                        compatible = "qcom,pcie-msm8996";
                        reg =   <0x01c00000 0x2000>,