]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
drm/i915: Use intel_ddi_dp_voltage_max() for HSW/BDW too
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Thu, 17 May 2018 17:03:05 +0000 (20:03 +0300)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Fri, 18 May 2018 14:23:40 +0000 (17:23 +0300)
Use intel_ddi_dp_voltage_max() for HSW/BDW too instead of letting these
fall through the if ladder in a weird way. This function will look at
the actual buf trans tables we have for HSW/BDW to determine the max
vswing level.

It looks to me like the current code leads HSW port A down the IVB port
A path, HSW port B+ and BDW fall through to the very end. Both cases do
result in the correct max vswing level 2, but it's very hard to see that
from the code.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180517170309.28630-1-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/intel_dp.c

index 2cc58596ff5ab099b3b22ec8a174aa63722743e4..4755bb1b0b4044e5b8eb0ca93cd2b50815e04467 100644 (file)
@@ -3220,12 +3220,12 @@ uint8_t
 intel_dp_voltage_max(struct intel_dp *intel_dp)
 {
        struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
-       enum port port = dp_to_dig_port(intel_dp)->base.port;
+       struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+       enum port port = encoder->port;
 
-       if (INTEL_GEN(dev_priv) >= 9) {
-               struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+       if (HAS_DDI(dev_priv))
                return intel_ddi_dp_voltage_max(encoder);
-       else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+       else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
                return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
        else if (IS_GEN7(dev_priv) && port == PORT_A)
                return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;