media: rcar-vin: enable support for r8a77965

Add the SoC specific information for Renesas r8a77965.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>

diff --git a/drivers/media/platform/rcar-vin/rcar-core.c b/drivers/media/platform/rcar-vin/rcar-core.c
index d3072e166a1ca24fd54248846a8ea924c0cc55d4..e6a010ee4ba1f671a70c58f47a99dd06a62ac9b8 100644 (file)
--- a/drivers/media/platform/rcar-vin/rcar-core.c
+++ b/drivers/media/platform/rcar-vin/rcar-core.c
@@ -974,6 +974,50 @@ static const struct rvin_info rcar_info_r8a7796 = {
        .routes = rcar_info_r8a7796_routes,
 };
 
+static const struct rvin_group_route rcar_info_r8a77965_routes[] = {
+       { .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) },
+       { .csi = RVIN_CSI20, .channel = 0, .vin = 0, .mask = BIT(1) | BIT(4) },
+       { .csi = RVIN_CSI40, .channel = 1, .vin = 0, .mask = BIT(2) },
+       { .csi = RVIN_CSI20, .channel = 0, .vin = 1, .mask = BIT(0) },
+       { .csi = RVIN_CSI40, .channel = 1, .vin = 1, .mask = BIT(1) | BIT(3) },
+       { .csi = RVIN_CSI40, .channel = 0, .vin = 1, .mask = BIT(2) },
+       { .csi = RVIN_CSI20, .channel = 1, .vin = 1, .mask = BIT(4) },
+       { .csi = RVIN_CSI20, .channel = 1, .vin = 2, .mask = BIT(0) },
+       { .csi = RVIN_CSI40, .channel = 0, .vin = 2, .mask = BIT(1) },
+       { .csi = RVIN_CSI20, .channel = 0, .vin = 2, .mask = BIT(2) },
+       { .csi = RVIN_CSI40, .channel = 2, .vin = 2, .mask = BIT(3) },
+       { .csi = RVIN_CSI20, .channel = 2, .vin = 2, .mask = BIT(4) },
+       { .csi = RVIN_CSI40, .channel = 1, .vin = 3, .mask = BIT(0) },
+       { .csi = RVIN_CSI20, .channel = 1, .vin = 3, .mask = BIT(1) | BIT(2) },
+       { .csi = RVIN_CSI40, .channel = 3, .vin = 3, .mask = BIT(3) },
+       { .csi = RVIN_CSI20, .channel = 3, .vin = 3, .mask = BIT(4) },
+       { .csi = RVIN_CSI40, .channel = 0, .vin = 4, .mask = BIT(0) | BIT(3) },
+       { .csi = RVIN_CSI20, .channel = 0, .vin = 4, .mask = BIT(1) | BIT(4) },
+       { .csi = RVIN_CSI40, .channel = 1, .vin = 4, .mask = BIT(2) },
+       { .csi = RVIN_CSI20, .channel = 0, .vin = 5, .mask = BIT(0) },
+       { .csi = RVIN_CSI40, .channel = 1, .vin = 5, .mask = BIT(1) | BIT(3) },
+       { .csi = RVIN_CSI40, .channel = 0, .vin = 5, .mask = BIT(2) },
+       { .csi = RVIN_CSI20, .channel = 1, .vin = 5, .mask = BIT(4) },
+       { .csi = RVIN_CSI20, .channel = 1, .vin = 6, .mask = BIT(0) },
+       { .csi = RVIN_CSI40, .channel = 0, .vin = 6, .mask = BIT(1) },
+       { .csi = RVIN_CSI20, .channel = 0, .vin = 6, .mask = BIT(2) },
+       { .csi = RVIN_CSI40, .channel = 2, .vin = 6, .mask = BIT(3) },
+       { .csi = RVIN_CSI20, .channel = 2, .vin = 6, .mask = BIT(4) },
+       { .csi = RVIN_CSI40, .channel = 1, .vin = 7, .mask = BIT(0) },
+       { .csi = RVIN_CSI20, .channel = 1, .vin = 7, .mask = BIT(1) | BIT(2) },
+       { .csi = RVIN_CSI40, .channel = 3, .vin = 7, .mask = BIT(3) },
+       { .csi = RVIN_CSI20, .channel = 3, .vin = 7, .mask = BIT(4) },
+       { /* Sentinel */ }
+};
+
+static const struct rvin_info rcar_info_r8a77965 = {
+       .model = RCAR_GEN3,
+       .use_mc = true,
+       .max_width = 4096,
+       .max_height = 4096,
+       .routes = rcar_info_r8a77965_routes,
+};
+
 static const struct rvin_group_route _rcar_info_r8a77970_routes[] = {
        { .csi = RVIN_CSI40, .channel = 0, .vin = 0, .mask = BIT(0) | BIT(3) },
        { .csi = RVIN_CSI40, .channel = 0, .vin = 1, .mask = BIT(2) },
@@ -1030,6 +1074,10 @@ static const struct of_device_id rvin_of_id_table[] = {
                .compatible = "renesas,vin-r8a7796",
                .data = &rcar_info_r8a7796,
        },
+       {
+               .compatible = "renesas,vin-r8a77965",
+               .data = &rcar_info_r8a77965,
+       },
        {
                .compatible = "renesas,vin-r8a77970",
                .data = &rcar_info_r8a77970,