]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
powerpc/kmcent2: add ranges to the pci bridges
authorValentin Longchamp <valentin@longchamp.me>
Tue, 12 Nov 2019 19:56:23 +0000 (20:56 +0100)
committerScott Wood <oss@buserror.net>
Sun, 17 Nov 2019 08:01:02 +0000 (02:01 -0600)
This removes the warnings about the fact that the 4 pci bridges (i.e.
the 4 pci hosts) don't have any ranges.

Signed-off-by: Valentin Longchamp <valentin@longchamp.me>
Signed-off-by: Scott Wood <oss@buserror.net>
arch/powerpc/boot/dts/fsl/kmcent2.dts

index c3e0741cafb1e5089d95d97b5af35300d9c07059..8e7f0828af295bd0c8ba80751cc7f92680df4922 100644 (file)
@@ -264,14 +264,50 @@ pcie@0 {
 
        pci1: pcie@ffe250000 {
                status = "disabled";
+               reg = <0xf 0xfe250000 0 0x10000>;
+               ranges = <0x02000000 0 0xe0000000 0xc 0x10000000 0 0x10000000
+                         0x01000000 0 0 0xf 0xf8010000 0 0x00010000>;
+               pcie@0 {
+                       ranges = <0x02000000 0 0xe0000000
+                                 0x02000000 0 0xe0000000
+                                 0 0x10000000
+
+                                 0x01000000 0 0x00000000
+                                 0x01000000 0 0x00000000
+                                 0 0x00010000>;
+               };
        };
 
        pci2: pcie@ffe260000 {
                status = "disabled";
+               reg = <0xf 0xfe260000 0 0x10000>;
+               ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000
+                         0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
+               pcie@0 {
+                       ranges = <0x02000000 0 0xe0000000
+                                 0x02000000 0 0xe0000000
+                                 0 0x10000000
+
+                                 0x01000000 0 0x00000000
+                                 0x01000000 0 0x00000000
+                                 0 0x00010000>;
+               };
        };
 
        pci3: pcie@ffe270000 {
                status = "disabled";
+               reg = <0xf 0xfe270000 0 0x10000>;
+               ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
+                         0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
+               pcie@0 {
+                       ranges = <0x02000000 0 0xe0000000
+                                 0x02000000 0 0xe0000000
+                                 0 0x10000000
+
+                                 0x01000000 0 0x00000000
+                                 0x01000000 0 0x00000000
+                                 0 0x00010000>;
+               };
        };
 
        qe: qe@ffe140000 {