]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
drm/amdgpu: use 2MB fragment size for GFX6,7 and 8
authorChristian König <christian.koenig@amd.com>
Mon, 18 Sep 2017 12:32:38 +0000 (14:32 +0200)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 26 Sep 2017 19:14:20 +0000 (15:14 -0400)
Use 2MB fragment size by default for older hardware generations as well.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: John Bridgman <john.bridgman@amd.com>
Reviewed-by: Roger He <Hongbo.He@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

index 5be9c83dfcf7d6b9ff169e5cb7b5fcde192b49cc..2d1f3f651e1f57dde1fd4040b95c4dec0cbf4408 100644 (file)
@@ -831,7 +831,7 @@ static int gmc_v6_0_sw_init(void *handle)
        if (r)
                return r;
 
-       amdgpu_vm_adjust_size(adev, 64, 4);
+       amdgpu_vm_adjust_size(adev, 64, 9);
        adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
 
        adev->mc.mc_mask = 0xffffffffffULL;
index eace9e7182c8a832d2b29984463f78fe05ca002c..2256277d102f3b39f742684eb179ff12c7be8216 100644 (file)
@@ -970,7 +970,7 @@ static int gmc_v7_0_sw_init(void *handle)
         * Currently set to 4GB ((1 << 20) 4k pages).
         * Max GPUVM size for cayman and SI is 40 bits.
         */
-       amdgpu_vm_adjust_size(adev, 64, 4);
+       amdgpu_vm_adjust_size(adev, 64, 9);
        adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
 
        /* Set the internal MC address mask
index 3b3326daf32b9b09b25914a58d023b391ca8e52a..114671b57004fe7d12dee863ffa9be53b1512d4d 100644 (file)
@@ -1067,7 +1067,7 @@ static int gmc_v8_0_sw_init(void *handle)
         * Currently set to 4GB ((1 << 20) 4k pages).
         * Max GPUVM size for cayman and SI is 40 bits.
         */
-       amdgpu_vm_adjust_size(adev, 64, 4);
+       amdgpu_vm_adjust_size(adev, 64, 9);
        adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
 
        /* Set the internal MC address mask