ARM: dts: imx: ventana: add PWM nodes for Ventana boards

Ventana boards have an off-board connector with signals that can be pinmuxed
as either GPIO or PWM. This patch adds pwm device-tree nodes in the disabled
state which the bootloader can decide to enable based on bootloader config.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
index dc0cebfe22d7b9a8f0500e1313c67ede2718234d..5cd16f2178b80fd955e8be48b776fb601afe606b 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
@@ -174,6 +174,24 @@ &pcie {
        status = "okay";
 };
 
+&pwm2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
+       status = "disabled";
+};
+
+&pwm3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
+       status = "disabled";
+};
+
+&pwm4 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
+       status = "disabled";
+};
+
 &uart1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart1>;
@@ -294,6 +312,24 @@ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26   0x1b0b1
                        >;
                };
 
+               pinctrl_pwm2: pwm2grp {
+                       fsl,pins = <
+                               MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
+                       >;
+               };
+
+               pinctrl_pwm3: pwm3grp {
+                       fsl,pins = <
+                               MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
+                       >;
+               };
+
+               pinctrl_pwm4: pwm4grp {
+                       fsl,pins = <
+                               MX6QDL_PAD_SD4_DAT2__PWM4_OUT           0x1b0b1
+                       >;
+               };
+
                pinctrl_uart1: uart1grp {
                        fsl,pins = <
                                MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1

diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
index 5478ab6b078eb7082bb45d5ce8c4fca0039cb2b0..1a250f3b845756102c728296fd9e0e182975d103 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -282,6 +282,18 @@ &pcie {
        status = "okay";
 };
 
+&pwm2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
+       status = "disabled";
+};
+
+&pwm3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
+       status = "disabled";
+};
+
 &pwm4 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pwm4>;
@@ -436,6 +448,18 @@ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26   0x1b0b1
                        >;
                };
 
+               pinctrl_pwm2: pwm2grp {
+                       fsl,pins = <
+                               MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
+                       >;
+               };
+
+               pinctrl_pwm3: pwm3grp {
+                       fsl,pins = <
+                               MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
+                       >;
+               };
+
                pinctrl_pwm4: pwm4grp {
                        fsl,pins = <
                                MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1

diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
index 8ccf5e4f32ead5697b2650514bdbf13756c8d4f0..e8375e173873edc5dc39ef011321cbbac9378f00 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -287,6 +287,18 @@ eth1: sky2@8 { /* MAC/PHY on bus 8 */
        };
 };
 
+&pwm2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
+       status = "disabled";
+};
+
+&pwm3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
+       status = "disabled";
+};
+
 &pwm4 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pwm4>;
@@ -442,6 +454,18 @@ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26   0x1b0b1
                        >;
                };
 
+               pinctrl_pwm2: pwm2grp {
+                       fsl,pins = <
+                               MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
+                       >;
+               };
+
+               pinctrl_pwm3: pwm3grp {
+                       fsl,pins = <
+                               MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
+                       >;
+               };
+
                pinctrl_pwm4: pwm4grp {
                        fsl,pins = <
                                MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1

diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
index 7b50b1e552801b93bb808e96038d9a6bd998da11..66983dc5cbdae8868b2f20ade01b3df1be44575d 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
@@ -378,6 +378,24 @@ eth1: sky2@8 { /* MAC/PHY on bus 8 */
        };
 };
 
+&pwm1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
+       status = "disabled";
+};
+
+&pwm2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
+       status = "disabled";
+};
+
+&pwm3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
+       status = "disabled";
+};
+
 &pwm4 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pwm4>;
@@ -537,6 +555,24 @@ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26   0x1b0b1
                        >;
                };
 
+               pinctrl_pwm1: pwm1grp {
+                       fsl,pins = <
+                               MX6QDL_PAD_GPIO_9__PWM1_OUT             0x1b0b1
+                       >;
+               };
+
+               pinctrl_pwm2: pwm2grp {
+                       fsl,pins = <
+                               MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
+                       >;
+               };
+
+               pinctrl_pwm3: pwm3grp {
+                       fsl,pins = <
+                               MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
+                       >;
+               };
+
                pinctrl_pwm4: pwm4grp {
                        fsl,pins = <
                                MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1

diff --git a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
index 741f3d529e3e23bcf3cb17160620fb30ae2c79dc..118bea524dab4220318c62a0d37edb3892556877 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
@@ -198,6 +198,18 @@ &pcie {
        status = "okay";
 };
 
+&pwm2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
+       status = "disabled";
+};
+
+&pwm3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
+       status = "disabled";
+};
+
 &ssi1 {
        status = "okay";
 };
@@ -290,6 +302,18 @@ MX6QDL_PAD_GPIO_0__GPIO1_IO00              0x1b0b0 /* PCIE RST */
                        >;
                };
 
+               pinctrl_pwm2: pwm2grp {
+                       fsl,pins = <
+                               MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
+                       >;
+               };
+
+               pinctrl_pwm3: pwm3grp {
+                       fsl,pins = <
+                               MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
+                       >;
+               };
+
                pinctrl_uart2: uart2grp {
                        fsl,pins = <
                                MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1

diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
index d1e5048b00b51c493b7843c7eba5d9e824269e86..cca39f194017c262d6c850172f76c584a73f099f 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
@@ -164,6 +164,18 @@ &pcie {
        status = "okay";
 };
 
+&pwm2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
+       status = "disabled";
+};
+
+&pwm3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
+       status = "disabled";
+};
+
 &uart2 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart2>;
@@ -242,6 +254,18 @@ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29   0x1b0b0
                        >;
                };
 
+               pinctrl_pwm2: pwm2grp {
+                       fsl,pins = <
+                               MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
+                       >;
+               };
+
+               pinctrl_pwm3: pwm3grp {
+                       fsl,pins = <
+                               MX6QDL_PAD_SD4_DAT1__PWM3_OUT           0x1b0b1
+                       >;
+               };
+
                pinctrl_uart2: uart2grp {
                        fsl,pins = <
                                MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1