PCI: xilinx: Don't enable config completion interrupts

The Xilinx AXI bridge for PCI Express device provides interrupts indicating
the completion of config space accesses. We have previously
enabled/unmasked them but do nothing with them besides acknowledge them.

Leave the interrupts masked in order to avoid servicing a large number of
pointless interrupts during boot.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Bharat Kumar Gogada <bharatku@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Ravikiran Gummaluri <rgummal@xilinx.com>

diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index a7880bed56fc04f31d0e02ce81361276a21546e0..f30d03309c7ff4494451aa80e60432b2dc29fe51 100644 (file)
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -60,6 +60,7 @@
 #define XILINX_PCIE_INTR_MST_SLVERR    BIT(27)
 #define XILINX_PCIE_INTR_MST_ERRP      BIT(28)
 #define XILINX_PCIE_IMR_ALL_MASK       0x1FF30FED
+#define XILINX_PCIE_IMR_ENABLE_MASK    0x1FF30F0D
 #define XILINX_PCIE_IDR_ALL_MASK       0xFFFFFFFF
 
 /* Root Port Error FIFO Read Register definitions */
@@ -554,8 +555,8 @@ static void xilinx_pcie_init_port(struct xilinx_pcie_port *port)
                         XILINX_PCIE_IMR_ALL_MASK,
                   XILINX_PCIE_REG_IDR);
 
-       /* Enable all interrupts */
-       pcie_write(port, XILINX_PCIE_IMR_ALL_MASK, XILINX_PCIE_REG_IMR);
+       /* Enable all interrupts we handle */
+       pcie_write(port, XILINX_PCIE_IMR_ENABLE_MASK, XILINX_PCIE_REG_IMR);
 
        /* Enable the Bridge enable bit */
        pcie_write(port, pcie_read(port, XILINX_PCIE_REG_RPSC) |