drm/i915: Make sure pipe interrupts are processed before turning off power well on BDW+

Starting from BDW the DE_PIPE interrupts for pipe B and C belong to the
relevant display power well. So we should make sure we've finished
processing them before turning off the power well.

The pipe interrupts shouldn't really happen at this point anymore since
we've already shut down the planes/pipes/whatnot, but being a bit
paranoid shouldn't hurt.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1455907651-16397-1-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d56c261ad8672955b0519928e28efebe2631dfd8..a9048e1b96e53f4d83e8f4f16c67f2a2f7be2e61 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3366,6 +3366,22 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
        spin_unlock_irq(&dev_priv->irq_lock);
 }
 
+void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
+                                    unsigned int pipe_mask)
+{
+       spin_lock_irq(&dev_priv->irq_lock);
+       if (pipe_mask & 1 << PIPE_A)
+               GEN8_IRQ_RESET_NDX(DE_PIPE, PIPE_A);
+       if (pipe_mask & 1 << PIPE_B)
+               GEN8_IRQ_RESET_NDX(DE_PIPE, PIPE_B);
+       if (pipe_mask & 1 << PIPE_C)
+               GEN8_IRQ_RESET_NDX(DE_PIPE, PIPE_C);
+       spin_unlock_irq(&dev_priv->irq_lock);
+
+       /* make sure we're done processing display irqs */
+       synchronize_irq(dev_priv->dev->irq);
+}
+
 static void cherryview_irq_preinstall(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c208ca630e99981e4dad8f52bf89cab740ac4d83..4852049c9ab372375e3f826b9c6d4d617e220ffe 100644 (file)
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -993,6 +993,8 @@ static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
 int intel_get_crtc_scanline(struct intel_crtc *crtc);
 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
                                     unsigned int pipe_mask);
+void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
+                                    unsigned int pipe_mask);
 
 /* intel_crt.c */
 void intel_crt_init(struct drm_device *dev);

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index ec4faae49b3f6a21208c1e87ca617950e6c06201..e2329768902c0d996f3712212de9f2689a3fd5e5 100644 (file)
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -284,6 +284,13 @@ static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
                                                1 << PIPE_C | 1 << PIPE_B);
 }
 
+static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv)
+{
+       if (IS_BROADWELL(dev_priv))
+               gen8_irq_power_well_pre_disable(dev_priv,
+                                               1 << PIPE_C | 1 << PIPE_B);
+}
+
 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
                                       struct i915_power_well *power_well)
 {
@@ -309,6 +316,14 @@ static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
        }
 }
 
+static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv,
+                                      struct i915_power_well *power_well)
+{
+       if (power_well->data == SKL_DISP_PW_2)
+               gen8_irq_power_well_pre_disable(dev_priv,
+                                               1 << PIPE_C | 1 << PIPE_B);
+}
+
 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
                               struct i915_power_well *power_well, bool enable)
 {
@@ -334,6 +349,7 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
 
        } else {
                if (enable_requested) {
+                       hsw_power_well_pre_disable(dev_priv);
                        I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
                        POSTING_READ(HSW_PWR_WELL_DRIVER);
                        DRM_DEBUG_KMS("Requesting to disable the power well\n");
@@ -709,6 +725,9 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
        state_mask = SKL_POWER_WELL_STATE(power_well->data);
        is_enabled = tmp & state_mask;
 
+       if (!enable && enable_requested)
+               skl_power_well_pre_disable(dev_priv, power_well);
+
        if (enable) {
                if (!enable_requested) {
                        WARN((tmp & state_mask) &&