drm/amd/display: Add Renoir hw_seq register list

These are the registers used to for the hw sequences
for modesetting.

Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 7d93babaa2fbd7e39e6708ef33cbb209b11cb438..b7767d6be1b4b86df5f8dd29cf6230444651d840 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -278,6 +278,59 @@
        BL_REG_LIST()
 #endif
 
+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+#define HWSEQ_DCN21_REG_LIST()\
+       HWSEQ_DCN_REG_LIST(), \
+       HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \
+       HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \
+       HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \
+       HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \
+       MMHUB_DCN_REG_LIST(), \
+       SR(MICROSECOND_TIME_BASE_DIV), \
+       SR(MILLISECOND_TIME_BASE_DIV), \
+       SR(DISPCLK_FREQ_CHANGE_CNTL), \
+       SR(RBBMIF_TIMEOUT_DIS), \
+       SR(RBBMIF_TIMEOUT_DIS_2), \
+       SR(DCHUBBUB_CRC_CTRL), \
+       SR(DPP_TOP0_DPP_CRC_CTRL), \
+       SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
+       SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
+       SR(MPC_CRC_CTRL), \
+       SR(MPC_CRC_RESULT_GB), \
+       SR(MPC_CRC_RESULT_C), \
+       SR(MPC_CRC_RESULT_AR), \
+       SR(DOMAIN0_PG_CONFIG), \
+       SR(DOMAIN1_PG_CONFIG), \
+       SR(DOMAIN2_PG_CONFIG), \
+       SR(DOMAIN3_PG_CONFIG), \
+       SR(DOMAIN4_PG_CONFIG), \
+       SR(DOMAIN5_PG_CONFIG), \
+       SR(DOMAIN6_PG_CONFIG), \
+       SR(DOMAIN7_PG_CONFIG), \
+       SR(DOMAIN16_PG_CONFIG), \
+       SR(DOMAIN17_PG_CONFIG), \
+       SR(DOMAIN18_PG_CONFIG), \
+       SR(DOMAIN0_PG_STATUS), \
+       SR(DOMAIN1_PG_STATUS), \
+       SR(DOMAIN2_PG_STATUS), \
+       SR(DOMAIN3_PG_STATUS), \
+       SR(DOMAIN4_PG_STATUS), \
+       SR(DOMAIN5_PG_STATUS), \
+       SR(DOMAIN6_PG_STATUS), \
+       SR(DOMAIN7_PG_STATUS), \
+       SR(DOMAIN16_PG_STATUS), \
+       SR(DOMAIN17_PG_STATUS), \
+       SR(DOMAIN18_PG_STATUS), \
+       SR(D1VGA_CONTROL), \
+       SR(D2VGA_CONTROL), \
+       SR(D3VGA_CONTROL), \
+       SR(D4VGA_CONTROL), \
+       SR(D5VGA_CONTROL), \
+       SR(D6VGA_CONTROL), \
+       SR(DC_IP_REQUEST_CNTL), \
+       BL_REG_LIST()
+#endif
+
 struct dce_hwseq_registers {
 
                /* Backlight registers */
@@ -586,6 +639,50 @@ struct dce_hwseq_registers {
        HWSEQ_LVTMA_MASK_SH_LIST(mask_sh)
 #endif
 
+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+#define HWSEQ_DCN21_MASK_SH_LIST(mask_sh)\
+       HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
+       HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
+       HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\
+       HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\
+       HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \
+       HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \
+       HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \
+       HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \
+       HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \
+       HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \
+       HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \
+       HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \
+       HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \
+       HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \
+       HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \
+       HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \
+       HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \
+       HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \
+       HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \
+       HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \
+       HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \
+       HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \
+       HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \
+       HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \
+       HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \
+       HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \
+       HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \
+       HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \
+       HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \
+       HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \
+       HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \
+       HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \
+       HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \
+       HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \
+       HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \
+       HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \
+       HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \
+       HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
+       HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
+       HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
+#endif
+
 #define HWSEQ_REG_FIELD_LIST(type) \
        type DCFE_CLOCK_ENABLE; \
        type DCFEV_CLOCK_ENABLE; \