]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
arm64: dts: allwinner: a64: enable DVFS
authorVasily Khoruzhick <anarsoul@gmail.com>
Wed, 8 Jan 2020 04:20:18 +0000 (20:20 -0800)
committerMaxime Ripard <maxime@cerno.tech>
Mon, 13 Jan 2020 08:54:53 +0000 (16:54 +0800)
Add CPU regulator and operating points for all the A64-based boards
that are currently supported to enable DVFS.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts
arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi
arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts

index ac979de190130b4bb4f744c9c7e0f1366b54c5e2..c7bd73f35ed89e917e2060d61aefd8b1603721c3 100644 (file)
@@ -5,6 +5,7 @@
 /dts-v1/;
 
 #include "sun50i-a64.dtsi"
+#include "sun50i-a64-cpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 
@@ -63,6 +64,22 @@ wifi_pwrseq: wifi-pwrseq {
        };
 };
 
+&cpu0 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu1 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu2 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu3 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
 &csi {
        status = "okay";
 
index 2e00c44c717814b8a2f9016033f5597a51b980da..883f217efb8121f49c05b4d63eb468edebf0aeda 100644 (file)
@@ -4,6 +4,7 @@
 /dts-v1/;
 
 #include "sun50i-a64.dtsi"
+#include "sun50i-a64-cpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 
@@ -69,6 +70,22 @@ &codec_analog {
        status = "okay";
 };
 
+&cpu0 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu1 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu2 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu3 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
 &dai {
        status = "okay";
 };
index e7b64a5f8c13f0ce3905840b2fd36be1afd96433..e58db8a6cab6969e344d92f9424cea236126ea3e 100644 (file)
@@ -4,6 +4,7 @@
 /dts-v1/;
 
 #include "sun50i-a64.dtsi"
+#include "sun50i-a64-cpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 
@@ -48,6 +49,22 @@ wifi_pwrseq: wifi_pwrseq {
        };
 };
 
+&cpu0 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu1 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu2 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu3 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
 &de {
        status = "okay";
 };
index d387d749a194f95ab78d4735e33307992abc50be..c52cf7ebf00c6b5843c7e43808b8f4727480c7f8 100644 (file)
@@ -4,6 +4,7 @@
 /dts-v1/;
 
 #include "sun50i-a64.dtsi"
+#include "sun50i-a64-cpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 
@@ -48,6 +49,22 @@ wifi_pwrseq: wifi_pwrseq {
        };
 };
 
+&cpu0 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu1 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu2 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu3 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
 &de {
        status = "okay";
 };
index 72120e45f35eb7a16b70f3fc4874374e8d62a259..fde9c7a99b17e5b116576d201145c097704a51f3 100644 (file)
@@ -5,6 +5,7 @@
 /dts-v1/;
 
 #include "sun50i-a64.dtsi"
+#include "sun50i-a64-cpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 
@@ -84,6 +85,22 @@ &codec_analog {
        status = "okay";
 };
 
+&cpu0 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu1 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu2 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu3 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
 &dai {
        status = "okay";
 };
index 6f817cfcccb958740e4a03d50411aa2ff695db9d..2165f238af13cc77a0a84ead3312a3886ef11646 100644 (file)
@@ -4,6 +4,7 @@
 /dts-v1/;
 
 #include "sun50i-a64.dtsi"
+#include "sun50i-a64-cpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 
@@ -45,6 +46,22 @@ &codec_analog {
        status = "okay";
 };
 
+&cpu0 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu1 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu2 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu3 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
 &dai {
        status = "okay";
 };
index b47147ee522d3ee75ad0264bc9256f719c386e3c..3d894b2089015b53116a791764f40d60babcee5d 100644 (file)
@@ -5,6 +5,7 @@
 /dts-v1/;
 
 #include "sun50i-a64.dtsi"
+#include "sun50i-a64-cpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/gpio-keys.h>
@@ -97,6 +98,22 @@ &codec_analog {
        status = "okay";
 };
 
+&cpu0 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu1 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu2 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu3 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
 &dai {
        status = "okay";
 };
index f1204fc4223c80473148a441d4444a32a3f13b86..c48692b06e1fa70a6e3263bf2a584172b3866f5f 100644 (file)
@@ -4,6 +4,7 @@
 //   Copyright (c) 2016 ARM Ltd.
 
 #include "sun50i-a64.dtsi"
+#include "sun50i-a64-cpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 
@@ -11,6 +12,22 @@ &codec_analog {
        cpvdd-supply = <&reg_eldo1>;
 };
 
+&cpu0 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu1 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu2 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu3 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
 &mmc0 {
        pinctrl-names = "default";
        pinctrl-0 = <&mmc0_pins>;
index 421454c8add7f83b3c325a672195b2bdc604e053..f5df5f705b72ae6dead0cfde7e672992030ea7bc 100644 (file)
@@ -5,6 +5,7 @@
 /dts-v1/;
 
 #include "sun50i-a64.dtsi"
+#include "sun50i-a64-cpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
@@ -101,6 +102,22 @@ &de {
        status = "okay";
 };
 
+&cpu0 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu1 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu2 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
+&cpu3 {
+       cpu-supply = <&reg_dcdc2>;
+};
+
 &ehci1 {
        status = "okay";
 };