crypto: ccp - Support register differences between PSP devices

In preparation for adding a new PSP device ID that uses different register
offsets, add support to the PSP version data for register offset values.
And then update the code to use these new register offset values.

Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Acked-by: Gary R Hook <gary.hook@amd.com>
Reviewed-by: Brijesh Singh <brijesh.singh@amd.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/ccp/psp-dev.c b/drivers/crypto/ccp/psp-dev.c
index 875756dd902455f874e5788d7ff1ec98bfbb29ca..9b596387a09faf0f95d63efc3a7fc473a49150b9 100644 (file)
--- a/drivers/crypto/ccp/psp-dev.c
+++ b/drivers/crypto/ccp/psp-dev.c
@@ -62,14 +62,14 @@ static irqreturn_t psp_irq_handler(int irq, void *data)
        int reg;
 
        /* Read the interrupt status: */
-       status = ioread32(psp->io_regs + PSP_P2CMSG_INTSTS);
+       status = ioread32(psp->io_regs + psp->vdata->intsts_reg);
 
        /* Check if it is command completion: */
        if (!(status & PSP_CMD_COMPLETE))
                goto done;
 
        /* Check if it is SEV command completion: */
-       reg = ioread32(psp->io_regs + PSP_CMDRESP);
+       reg = ioread32(psp->io_regs + psp->vdata->cmdresp_reg);
        if (reg & PSP_CMDRESP_RESP) {
                psp->sev_int_rcvd = 1;
                wake_up(&psp->sev_int_queue);
@@ -77,7 +77,7 @@ static irqreturn_t psp_irq_handler(int irq, void *data)
 
 done:
        /* Clear the interrupt status by writing the same value we read. */
-       iowrite32(status, psp->io_regs + PSP_P2CMSG_INTSTS);
+       iowrite32(status, psp->io_regs + psp->vdata->intsts_reg);
 
        return IRQ_HANDLED;
 }
@@ -85,7 +85,7 @@ static irqreturn_t psp_irq_handler(int irq, void *data)
 static void sev_wait_cmd_ioc(struct psp_device *psp, unsigned int *reg)
 {
        wait_event(psp->sev_int_queue, psp->sev_int_rcvd);
-       *reg = ioread32(psp->io_regs + PSP_CMDRESP);
+       *reg = ioread32(psp->io_regs + psp->vdata->cmdresp_reg);
 }
 
 static int sev_cmd_buffer_len(int cmd)
@@ -143,15 +143,15 @@ static int __sev_do_cmd_locked(int cmd, void *data, int *psp_ret)
        print_hex_dump_debug("(in):  ", DUMP_PREFIX_OFFSET, 16, 2, data,
                             sev_cmd_buffer_len(cmd), false);
 
-       iowrite32(phys_lsb, psp->io_regs + PSP_CMDBUFF_ADDR_LO);
-       iowrite32(phys_msb, psp->io_regs + PSP_CMDBUFF_ADDR_HI);
+       iowrite32(phys_lsb, psp->io_regs + psp->vdata->cmdbuff_addr_lo_reg);
+       iowrite32(phys_msb, psp->io_regs + psp->vdata->cmdbuff_addr_hi_reg);
 
        psp->sev_int_rcvd = 0;
 
        reg = cmd;
        reg <<= PSP_CMDRESP_CMD_SHIFT;
        reg |= PSP_CMDRESP_IOC;
-       iowrite32(reg, psp->io_regs + PSP_CMDRESP);
+       iowrite32(reg, psp->io_regs + psp->vdata->cmdresp_reg);
 
        /* wait for command completion */
        sev_wait_cmd_ioc(psp, &reg);
@@ -789,7 +789,7 @@ static int sev_misc_init(struct psp_device *psp)
 static int sev_init(struct psp_device *psp)
 {
        /* Check if device supports SEV feature */
-       if (!(ioread32(psp->io_regs + PSP_FEATURE_REG) & 1)) {
+       if (!(ioread32(psp->io_regs + psp->vdata->feature_reg) & 1)) {
                dev_dbg(psp->dev, "device does not support SEV\n");
                return 1;
        }
@@ -817,11 +817,11 @@ int psp_dev_init(struct sp_device *sp)
                goto e_err;
        }
 
-       psp->io_regs = sp->io_map + psp->vdata->offset;
+       psp->io_regs = sp->io_map;
 
        /* Disable and clear interrupts until ready */
-       iowrite32(0, psp->io_regs + PSP_P2CMSG_INTEN);
-       iowrite32(-1, psp->io_regs + PSP_P2CMSG_INTSTS);
+       iowrite32(0, psp->io_regs + psp->vdata->inten_reg);
+       iowrite32(-1, psp->io_regs + psp->vdata->intsts_reg);
 
        /* Request an irq */
        ret = sp_request_psp_irq(psp->sp, psp_irq_handler, psp->name, psp);
@@ -838,7 +838,7 @@ int psp_dev_init(struct sp_device *sp)
                sp->set_psp_master_device(sp);
 
        /* Enable interrupt */
-       iowrite32(-1, psp->io_regs + PSP_P2CMSG_INTEN);
+       iowrite32(-1, psp->io_regs + psp->vdata->inten_reg);
 
        dev_notice(dev, "psp enabled\n");
 

diff --git a/drivers/crypto/ccp/psp-dev.h b/drivers/crypto/ccp/psp-dev.h
index 5d46a2bebfd1012a0a9d46590dcab2b6c7010eb1..8b53a9674ecba02b864faef89f238cf770374bf2 100644 (file)
--- a/drivers/crypto/ccp/psp-dev.h
+++ b/drivers/crypto/ccp/psp-dev.h
@@ -30,17 +30,8 @@
 
 #include "sp-dev.h"
 
-#define PSP_C2PMSG(_num)               ((_num) << 2)
-#define PSP_CMDRESP                    PSP_C2PMSG(32)
-#define PSP_CMDBUFF_ADDR_LO            PSP_C2PMSG(56)
-#define PSP_CMDBUFF_ADDR_HI             PSP_C2PMSG(57)
-#define PSP_FEATURE_REG                        PSP_C2PMSG(63)
-
 #define PSP_CMD_COMPLETE               BIT(1)
 
-#define PSP_P2CMSG_INTEN               0x0110
-#define PSP_P2CMSG_INTSTS              0x0114
-
 #define PSP_CMDRESP_CMD_SHIFT          16
 #define PSP_CMDRESP_IOC                        BIT(0)
 #define PSP_CMDRESP_RESP               BIT(31)

diff --git a/drivers/crypto/ccp/sp-dev.h b/drivers/crypto/ccp/sp-dev.h
index acb197b66ced9744ef6f22710003413c869caf1b..14398cad16257b75a0a28f69df313e7b8a6831e7 100644 (file)
--- a/drivers/crypto/ccp/sp-dev.h
+++ b/drivers/crypto/ccp/sp-dev.h
@@ -44,7 +44,12 @@ struct ccp_vdata {
 };
 
 struct psp_vdata {
-       const unsigned int offset;
+       const unsigned int cmdresp_reg;
+       const unsigned int cmdbuff_addr_lo_reg;
+       const unsigned int cmdbuff_addr_hi_reg;
+       const unsigned int feature_reg;
+       const unsigned int inten_reg;
+       const unsigned int intsts_reg;
 };
 
 /* Structure to hold SP device data */

diff --git a/drivers/crypto/ccp/sp-pci.c b/drivers/crypto/ccp/sp-pci.c
index f5f43c50698ac4e2fa3cea375d73bc000290f27d..78c1e9d606c9bff3a5117453b58427599fc62127 100644 (file)
--- a/drivers/crypto/ccp/sp-pci.c
+++ b/drivers/crypto/ccp/sp-pci.c
@@ -270,7 +270,12 @@ static int sp_pci_resume(struct pci_dev *pdev)
 
 #ifdef CONFIG_CRYPTO_DEV_SP_PSP
 static const struct psp_vdata psp_entry = {
-       .offset = 0x10500,
+       .cmdresp_reg            = 0x10580,
+       .cmdbuff_addr_lo_reg    = 0x105e0,
+       .cmdbuff_addr_hi_reg    = 0x105e4,
+       .feature_reg            = 0x105fc,
+       .inten_reg              = 0x10610,
+       .intsts_reg             = 0x10614,
 };
 #endif