PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of SoC struct

Tegra186 and Tegra30 have three PCIe root ports. AFI_PEX2_CTRL register
is defined for third root port. Offset of this register in Tegra186 is
different from Tegra30, so add the offset as part of SoC data structure.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
index adc50daca9fb1ddb5b10ee2f87bee5b3f9561051..6be4ea72da92f70b1dffb3a09335f724a07684c9 100644 (file)
--- a/drivers/pci/controller/pci-tegra.c
+++ b/drivers/pci/controller/pci-tegra.c
@@ -168,7 +168,6 @@
 
 #define AFI_PEX0_CTRL                  0x110
 #define AFI_PEX1_CTRL                  0x118
-#define AFI_PEX2_CTRL                  0x128
 #define  AFI_PEX_CTRL_RST              (1 << 0)
 #define  AFI_PEX_CTRL_CLKREQ_EN                (1 << 1)
 #define  AFI_PEX_CTRL_REFCLK_EN                (1 << 3)
@@ -307,6 +306,7 @@ struct tegra_pcie_soc {
        unsigned int num_ports;
        const struct tegra_pcie_port_soc *ports;
        unsigned int msi_base_shift;
+       unsigned long afi_pex2_ctrl;
        u32 pads_pll_ctl;
        u32 tx_ref_sel;
        u32 pads_refclk_cfg0;
@@ -517,6 +517,7 @@ static struct pci_ops tegra_pcie_ops = {
 
 static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
 {
+       const struct tegra_pcie_soc *soc = port->pcie->soc;
        unsigned long ret = 0;
 
        switch (port->index) {
@@ -529,7 +530,7 @@ static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
                break;
 
        case 2:
-               ret = AFI_PEX2_CTRL;
+               ret = soc->afi_pex2_ctrl;
                break;
        }
 
@@ -2449,6 +2450,7 @@ static const struct tegra_pcie_soc tegra20_pcie = {
        .num_ports = 2,
        .ports = tegra20_pcie_ports,
        .msi_base_shift = 0,
+       .afi_pex2_ctrl = 0x128,
        .pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
        .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
        .pads_refclk_cfg0 = 0xfa5cfa5c,
@@ -2566,6 +2568,7 @@ static const struct tegra_pcie_soc tegra186_pcie = {
        .num_ports = 3,
        .ports = tegra186_pcie_ports,
        .msi_base_shift = 8,
+       .afi_pex2_ctrl = 0x19c,
        .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
        .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
        .pads_refclk_cfg0 = 0x80b880b8,