drm/msm/adreno: Enable 64 bit mode by default on a5xx and a6xx targets

A5XX and newer GPUs can be run in either 32 or 64 bit mode. The GPU
registers and the microcode use 64 bit virtual addressing in either
case but the upper 32 bits are ignored if the GPU is in 32 bit mode.
There is no performance disadvantage to remaining in 64 bit mode even
if we are only generating 32 bit addresses so switch over now to prepare
for using addresses above 4G on targets that support them.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index e5fcefa49f19a6c70a2be35cf12b84ef77295c89..43a2b4a3b5d3846f2f0b4083c6706d1fce868577 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -642,6 +642,20 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
                REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI, 0x00000000);
        gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000);
 
+       /* Put the GPU into 64 bit by default */
+       gpu_write(gpu, REG_A5XX_CP_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A5XX_VSC_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A5XX_GRAS_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A5XX_RB_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A5XX_PC_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A5XX_HLSQ_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A5XX_VFD_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A5XX_VPC_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A5XX_UCHE_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A5XX_SP_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A5XX_TPL1_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);
+
        ret = adreno_hw_init(gpu);
        if (ret)
                return ret;

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 1f9f4b0a96565a0300f0e810b6b6e76d3f22ca79..be39cf01e51ecf73cf28bde06c3f6b6480207c80 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -391,6 +391,20 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
                REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI, 0x00000000);
        gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000);
 
+       /* Turn on 64 bit addressing for all blocks */
+       gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1);
+       gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);
+
        /* enable hardware clockgating */
        a6xx_set_hwcg(gpu, true);