arm: zynq: timer: Remove unnecessary register write

Acknowedging an interrupt requires to read the interrupt register
only. The write was only required to work around a bug in
the QEMU implementation of the TTC, which is fixed.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Tested-by: Josh Cartwright <josh.cartwright@ni.com>

diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c
index 570491d3796609ad61cc9b5512509fd8d3d9edc9..f1d224bf162d033588e55105a445bd7ad93477b8 100644 (file)
--- a/arch/arm/mach-zynq/timer.c
+++ b/arch/arm/mach-zynq/timer.c
@@ -121,8 +121,7 @@ static irqreturn_t xttcps_clock_event_interrupt(int irq, void *dev_id)
        struct xttcps_timer *timer = &xttce->xttc;
 
        /* Acknowledge the interrupt and call event handler */
-       __raw_writel(__raw_readl(timer->base_addr + XTTCPS_ISR_OFFSET),
-                       timer->base_addr + XTTCPS_ISR_OFFSET);
+       __raw_readl(timer->base_addr + XTTCPS_ISR_OFFSET);
 
        xttce->ce.event_handler(&xttce->ce);