ARM: dts: imx: add SPI to GW54xx

The GW54xx revision E adds SPI via an off-board connector.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
index 1753ab720b0be2676f90e2fe6c8a16dbee9925ab..1cdb2a79fa8260601374822cd8f43cf596cf65ac 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
@@ -149,6 +149,14 @@ &clks {
                                 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
 };
 
+&ecspi2 {
+       fsl,spi-num-chipselects = <1>;
+       cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ecspi2>;
+       status = "okay";
+};
+
 &fec {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet>;
@@ -499,6 +507,15 @@ MX6QDL_PAD_GPIO_16__ENET_REF_CLK   0x4001b0a8
                        >;
                };
 
+               pinctrl_ecspi2: escpi2grp {
+                       fsl,pins = <
+                               MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
+                               MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
+                               MX6QDL_PAD_EIM_OE__ECSPI2_MISO  0x100b1
+                               MX6QDL_PAD_EIM_RW__GPIO2_IO26   0x100b1
+                       >;
+               };
+
                pinctrl_flexcan1: flexcan1grp {
                        fsl,pins = <
                                MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b1