ahci: Add support for Cavium's fifth generation SATA controller

This patch adds support for Cavium's fifth generation SATA controller.
It is an on-chip controller and complies with AHCI 1.3.1. As the
controller uses 64-bit addresses it cannot use the standard AHCI BAR5
and so uses BAR4.

Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
Signed-off-by: Tejun Heo <tj@kernel.org>

diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index cb9b0e9090e3b8ec7e32fff751b1e34332cb7068..6e26c1c2d18cbc51169aad151cb9693d235c878c 100644 (file)
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -57,6 +57,7 @@ enum {
        AHCI_PCI_BAR_STA2X11    = 0,
        AHCI_PCI_BAR_CAVIUM     = 0,
        AHCI_PCI_BAR_ENMOTUS    = 2,
+       AHCI_PCI_BAR_CAVIUM_GEN5        = 4,
        AHCI_PCI_BAR_STANDARD   = 5,
 };
 
@@ -1567,8 +1568,12 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
                ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
        else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
                ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
-       else if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
-               ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
+       else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
+               if (pdev->device == 0xa01c)
+                       ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
+               if (pdev->device == 0xa084)
+                       ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
+       }
 
        /* acquire resources */
        rc = pcim_enable_device(pdev);