drm/amdgpu: adjust HDP write queue flushing for tlb invalidation

Separate tlb invalidation and hdp flushing and move the HDP
flush to the caller.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
index 0a4f34afaaaa321dc2a0680a227660d8ecefd0d3..d0617f1c252f99e648dbed8309bd762d1f4f4084 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
@@ -247,6 +247,7 @@ int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
                }
        }
        mb();
+       amdgpu_asic_flush_hdp(adev);
        amdgpu_gart_flush_gpu_tlb(adev, 0);
        return 0;
 }
@@ -329,6 +330,7 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
                return r;
 
        mb();
+       amdgpu_asic_flush_hdp(adev);
        amdgpu_gart_flush_gpu_tlb(adev, 0);
        return 0;
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 5afbc5e714d0849b43389d6c0cd8e360d4c72b47..df0f99741b736ee2828f606233427d7800db46c9 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -856,6 +856,7 @@ int amdgpu_vm_update_directories(struct amdgpu_device *adev,
        if (vm->use_cpu_for_update) {
                /* Flush HDP */
                mb();
+               amdgpu_asic_flush_hdp(adev);
                amdgpu_gart_flush_gpu_tlb(adev, 0);
        } else if (params.ib->length_dw == 0) {
                amdgpu_job_free(job);
@@ -1457,6 +1458,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
        if (vm->use_cpu_for_update) {
                /* Flush HDP */
                mb();
+               amdgpu_asic_flush_hdp(adev);
                amdgpu_gart_flush_gpu_tlb(adev, 0);
        }
 

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 5f5eb15ccf4ad336e12f30f89ab750c0f6afc28f..aa06e7232d2922cbdcca9b0e40e0979069251812 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -360,8 +360,6 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
 static void gmc_v6_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
                                        uint32_t vmid)
 {
-       WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
-
        WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 }
 

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 12e49bd8fd2da33ad608b1f56d5c2b5de941d9f7..550abff5cb12e265164f24258e9b0fd636450077 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -432,9 +432,6 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
 static void gmc_v7_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
                                        uint32_t vmid)
 {
-       /* flush hdp cache */
-       WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
-
        /* bits 0-15 are the VM contexts0-15 */
        WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 9a170e37fbe7598f84bada7ce582148db34d2cc3..c0ddd0f35b3b7bf46dd18b6c6e3737ef33cdc211 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -607,9 +607,6 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
 static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
                                        uint32_t vmid)
 {
-       /* flush hdp cache */
-       WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
-
        /* bits 0-15 are the VM contexts0-15 */
        WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 100ec69f020a67a473aa2a8da57de19a8a5b485c..2a565a48bd4f0890ad6cd1bed3c0b88d749147e5 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -330,9 +330,6 @@ static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev,
        const unsigned eng = 17;
        unsigned i, j;
 
-       /* flush hdp cache */
-       adev->nbio_funcs->hdp_flush(adev);
-
        spin_lock(&adev->mc.invalidate_lock);
 
        for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) {