]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
drm/amdgpu: add vcn jpeg ring test
authorBoyuan Zhang <boyuan.zhang@amd.com>
Wed, 30 May 2018 19:49:51 +0000 (15:49 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 15 Jun 2018 17:20:38 +0000 (12:20 -0500)
Add a ring test for vcn jpeg.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

index d485a74de44d86f3a67bd820a0134c70efc6bf10..0b97a72cc2021018d23e8ffcbab915d0675d49a6 100644 (file)
@@ -578,3 +578,43 @@ int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
        dma_fence_put(fence);
        return r;
 }
+
+int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring)
+{
+       struct amdgpu_device *adev = ring->adev;
+       uint32_t tmp = 0;
+       unsigned i;
+       int r;
+
+       WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0xCAFEDEAD);
+       r = amdgpu_ring_alloc(ring, 3);
+
+       if (r) {
+               DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
+                                 ring->idx, r);
+               return r;
+       }
+
+       amdgpu_ring_write(ring,
+               PACKETJ(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0, 0, 0));
+       amdgpu_ring_write(ring, 0xDEADBEEF);
+       amdgpu_ring_commit(ring);
+
+       for (i = 0; i < adev->usec_timeout; i++) {
+               tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID));
+               if (tmp == 0xDEADBEEF)
+                       break;
+               DRM_UDELAY(1);
+       }
+
+       if (i < adev->usec_timeout) {
+               DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
+                                 ring->idx, i);
+       } else {
+               DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
+                                 ring->idx, tmp);
+               r = -EINVAL;
+       }
+
+       return r;
+}
index 6f3bed1cc1b3eeffdffcd209ea03ee336e9650f0..0447faefb95abf70f73029933af9543738c56dc6 100644 (file)
@@ -84,4 +84,6 @@ int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring);
 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout);
 
+int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring);
+
 #endif
index 32b70049fd918afed99c52f5adc9bcca338eaaae..5fc58de0c4026a319e4166342e69ad32b7b35b77 100644 (file)
@@ -1712,7 +1712,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_jpeg_ring_vm_funcs = {
        .emit_ib = vcn_v1_0_jpeg_ring_emit_ib,
        .emit_fence = vcn_v1_0_jpeg_ring_emit_fence,
        .emit_vm_flush = vcn_v1_0_jpeg_ring_emit_vm_flush,
-       //.test_ring
+       .test_ring = amdgpu_vcn_jpeg_ring_test_ring,
        //.test_ib
        .insert_nop = vcn_v1_0_jpeg_ring_nop,
        .insert_start = vcn_v1_0_jpeg_ring_insert_start,