habanalabs: rename goya_non_fatal_events array to all events

The goya_non_fatal_events array actually contains all the possible events
the driver can receive from the F/W. Therefore, use a proper name
for the array.

The patch also adds missing event Ids to the goya_async_event_id enum.

Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>

diff --git a/drivers/misc/habanalabs/goya/goya.c b/drivers/misc/habanalabs/goya/goya.c
index 0185f11c5577768e5a967fc5024bb7e40cb47e1d..3dfac5393269ff132154618270e3c2473ef5cdf9 100644 (file)
--- a/drivers/misc/habanalabs/goya/goya.c
+++ b/drivers/misc/habanalabs/goya/goya.c
@@ -176,9 +176,7 @@ static u64 goya_mmu_regs[GOYA_MMU_REGS_NUM] = {
        mmMME_WBC_CONTROL_DATA
 };
 
-#define GOYA_ASYC_EVENT_GROUP_NON_FATAL_SIZE 121
-
-static u32 goya_non_fatal_events[GOYA_ASYC_EVENT_GROUP_NON_FATAL_SIZE] = {
+static u32 goya_all_events[] = {
        GOYA_ASYNC_EVENT_ID_PCIE_IF,
        GOYA_ASYNC_EVENT_ID_TPC0_ECC,
        GOYA_ASYNC_EVENT_ID_TPC1_ECC,
@@ -4627,8 +4625,8 @@ static int goya_soft_reset_late_init(struct hl_device *hdev)
         * Unmask all IRQs since some could have been received
         * during the soft reset
         */
-       return goya_unmask_irq_arr(hdev, goya_non_fatal_events,
-                       sizeof(goya_non_fatal_events));
+       return goya_unmask_irq_arr(hdev, goya_all_events,
+                                       sizeof(goya_all_events));
 }
 
 static int goya_unmask_irq(struct hl_device *hdev, u16 event_type)

diff --git a/drivers/misc/habanalabs/include/goya/goya_async_events.h b/drivers/misc/habanalabs/include/goya/goya_async_events.h
index 497937a17ee9b51fd7846ce47d4f79239d896c76..bb7a1aa3279ebb468661b222f70b6e393a31c468 100644 (file)
--- a/drivers/misc/habanalabs/include/goya/goya_async_events.h
+++ b/drivers/misc/habanalabs/include/goya/goya_async_events.h
@@ -9,7 +9,9 @@
 #define __GOYA_ASYNC_EVENTS_H_
 
 enum goya_async_event_id {
+       GOYA_ASYNC_EVENT_ID_PCIE_CORE = 32,
        GOYA_ASYNC_EVENT_ID_PCIE_IF = 33,
+       GOYA_ASYNC_EVENT_ID_PCIE_PHY = 34,
        GOYA_ASYNC_EVENT_ID_TPC0_ECC = 36,
        GOYA_ASYNC_EVENT_ID_TPC1_ECC = 39,
        GOYA_ASYNC_EVENT_ID_TPC2_ECC = 42,
@@ -23,6 +25,8 @@ enum goya_async_event_id {
        GOYA_ASYNC_EVENT_ID_MMU_ECC = 63,
        GOYA_ASYNC_EVENT_ID_DMA_MACRO = 64,
        GOYA_ASYNC_EVENT_ID_DMA_ECC = 66,
+       GOYA_ASYNC_EVENT_ID_DDR0_PARITY = 69,
+       GOYA_ASYNC_EVENT_ID_DDR1_PARITY = 72,
        GOYA_ASYNC_EVENT_ID_CPU_IF_ECC = 75,
        GOYA_ASYNC_EVENT_ID_PSOC_MEM = 78,
        GOYA_ASYNC_EVENT_ID_PSOC_CORESIGHT = 79,
@@ -72,6 +76,7 @@ enum goya_async_event_id {
        GOYA_ASYNC_EVENT_ID_MME_WACSD = 142,
        GOYA_ASYNC_EVENT_ID_PLL0 = 143,
        GOYA_ASYNC_EVENT_ID_PLL1 = 144,
+       GOYA_ASYNC_EVENT_ID_PLL2 = 145,
        GOYA_ASYNC_EVENT_ID_PLL3 = 146,
        GOYA_ASYNC_EVENT_ID_PLL4 = 147,
        GOYA_ASYNC_EVENT_ID_PLL5 = 148,
@@ -81,6 +86,7 @@ enum goya_async_event_id {
        GOYA_ASYNC_EVENT_ID_PSOC = 160,
        GOYA_ASYNC_EVENT_ID_PCIE_FLR = 171,
        GOYA_ASYNC_EVENT_ID_PCIE_HOT_RESET = 172,
+       GOYA_ASYNC_EVENT_ID_PCIE_PERST = 173,
        GOYA_ASYNC_EVENT_ID_PCIE_QID0_ENG0 = 174,
        GOYA_ASYNC_EVENT_ID_PCIE_QID0_ENG1 = 175,
        GOYA_ASYNC_EVENT_ID_PCIE_QID0_ENG2 = 176,
@@ -144,8 +150,11 @@ enum goya_async_event_id {
        GOYA_ASYNC_EVENT_ID_PSOC_GPIO_U16_0 = 330,
        GOYA_ASYNC_EVENT_ID_PSOC_GPIO_U16_1 = 331,
        GOYA_ASYNC_EVENT_ID_PSOC_GPIO_U16_2 = 332,
+       GOYA_ASYNC_EVENT_ID_PSOC_GPIO_U16_3 = 333,
+       GOYA_ASYNC_EVENT_ID_PSOC_GPIO_U16_4 = 334,
        GOYA_ASYNC_EVENT_ID_PSOC_GPIO_05_SW_RESET = 356,
        GOYA_ASYNC_EVENT_ID_PSOC_GPIO_10_VRHOT_ICRIT = 361,
+       GOYA_ASYNC_EVENT_ID_FAN = 425,
        GOYA_ASYNC_EVENT_ID_TPC0_CMDQ = 430,
        GOYA_ASYNC_EVENT_ID_TPC1_CMDQ = 431,
        GOYA_ASYNC_EVENT_ID_TPC2_CMDQ = 432,