]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
drm/amd/powerplay: helper interfaces for MGPU fan boost feature
authorEvan Quan <evan.quan@amd.com>
Thu, 27 Sep 2018 05:43:16 +0000 (13:43 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 9 Oct 2018 21:59:56 +0000 (16:59 -0500)
MGPU fan boost feature is enabled only when two or more dGPUs
in the system.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
drivers/gpu/drm/amd/include/kgd_pp_interface.h
drivers/gpu/drm/amd/powerplay/amd_powerplay.c
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h

index bd79d0a31942cea58c3f1a8094d2dff6c42a86fd..a1d8d97252e0cc5c2e4301115e87ae1703cf4e9e 100644 (file)
@@ -1833,6 +1833,43 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
        return 0;
 }
 
+static int amdgpu_device_enable_mgpu_fan_boost(void)
+{
+       struct amdgpu_gpu_instance *gpu_ins;
+       struct amdgpu_device *adev;
+       int i, ret = 0;
+
+       mutex_lock(&mgpu_info.mutex);
+
+       /*
+        * MGPU fan boost feature should be enabled
+        * only when there are two or more dGPUs in
+        * the system
+        */
+       if (mgpu_info.num_dgpu < 2)
+               goto out;
+
+       for (i = 0; i < mgpu_info.num_dgpu; i++) {
+               gpu_ins = &(mgpu_info.gpu_ins[i]);
+               adev = gpu_ins->adev;
+               if (!(adev->flags & AMD_IS_APU) &&
+                   !gpu_ins->mgpu_fan_enabled &&
+                   adev->powerplay.pp_funcs &&
+                   adev->powerplay.pp_funcs->enable_mgpu_fan_boost) {
+                       ret = amdgpu_dpm_enable_mgpu_fan_boost(adev);
+                       if (ret)
+                               break;
+
+                       gpu_ins->mgpu_fan_enabled = 1;
+               }
+       }
+
+out:
+       mutex_unlock(&mgpu_info.mutex);
+
+       return ret;
+}
+
 /**
  * amdgpu_device_ip_late_init_func_handler - work handler for ib test
  *
@@ -1847,6 +1884,10 @@ static void amdgpu_device_ip_late_init_func_handler(struct work_struct *work)
        r = amdgpu_ib_ring_tests(adev);
        if (r)
                DRM_ERROR("ib ring test failed (%d).\n", r);
+
+       r = amdgpu_device_enable_mgpu_fan_boost();
+       if (r)
+               DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
 }
 
 static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work)
index ff24e1cc5b65bd66e4657e833a97e1d18ae4d2b3..42568ae6b9f4a6a0275483839c63b4242208ed7f 100644 (file)
@@ -357,6 +357,10 @@ enum amdgpu_pcie_gen {
                ((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\
                        (adev)->powerplay.pp_handle, type, parameter, size))
 
+#define amdgpu_dpm_enable_mgpu_fan_boost(adev) \
+               ((adev)->powerplay.pp_funcs->enable_mgpu_fan_boost(\
+                       (adev)->powerplay.pp_handle))
+
 struct amdgpu_dpm {
        struct amdgpu_ps        *ps;
        /* number of valid power states */
index bd7404532029577ac80da9ecb3814502524c39d1..8593850920d68edce42ebc38190eae2a567cf112 100644 (file)
@@ -272,6 +272,7 @@ struct amd_pm_funcs {
        int (*get_display_mode_validation_clocks)(void *handle,
                struct amd_pp_simple_clock_info *clocks);
        int (*notify_smu_enable_pwe)(void *handle);
+       int (*enable_mgpu_fan_boost)(void *handle);
 };
 
 #endif
index da4ebff5b74d75bb62270428426746eb2acb8b49..c2e5412662737d36818007703db4747a8b8ce7f8 100644 (file)
@@ -1243,6 +1243,24 @@ static int pp_notify_smu_enable_pwe(void *handle)
        return 0;
 }
 
+static int pp_enable_mgpu_fan_boost(void *handle)
+{
+       struct pp_hwmgr *hwmgr = handle;
+
+       if (!hwmgr || !hwmgr->pm_en)
+               return -EINVAL;
+
+       if (hwmgr->hwmgr_func->enable_mgpu_fan_boost == NULL) {
+               return 0;
+       }
+
+       mutex_lock(&hwmgr->smu_lock);
+       hwmgr->hwmgr_func->enable_mgpu_fan_boost(hwmgr);
+       mutex_unlock(&hwmgr->smu_lock);
+
+       return 0;
+}
+
 static const struct amd_pm_funcs pp_dpm_funcs = {
        .load_firmware = pp_dpm_load_fw,
        .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
@@ -1287,4 +1305,5 @@ static const struct amd_pm_funcs pp_dpm_funcs = {
        .display_clock_voltage_request = pp_display_clock_voltage_request,
        .get_display_mode_validation_clocks = pp_get_display_mode_validation_clocks,
        .notify_smu_enable_pwe = pp_notify_smu_enable_pwe,
+       .enable_mgpu_fan_boost = pp_enable_mgpu_fan_boost,
 };
index a6d92128b19cc8dbb45625d0321fa85a81469db1..8484e2db2554a7096de1e5337c84868fd8d473e2 100644 (file)
@@ -328,6 +328,7 @@ struct pp_hwmgr_func {
        int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n);
        int (*powergate_mmhub)(struct pp_hwmgr *hwmgr);
        int (*smus_notify_pwe)(struct pp_hwmgr *hwmgr);
+       int (*enable_mgpu_fan_boost)(struct pp_hwmgr *hwmgr);
 };
 
 struct pp_table_func {