drm/msm/dsi: Move PHY operations out of host

Since DSI PHY has been a separate platform device, it should not
depend on the resources in host to be functional. This change is
to trigger PHY operations in manager, instead of host, so that
host and PHY can be completely separated.

Signed-off-by: Hai Li <hali@codeaurora.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>

diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 9407a682d04540d23bcb4091bb3e1410d5bf3a87..9465996d0869ad70ccf434ec8a8b81a50c50cd70 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -28,6 +28,7 @@
 #define DSI_MAX        2
 
 struct msm_dsi_phy_shared_timings;
+struct msm_dsi_phy_clk_request;
 
 enum msm_dsi_phy_type {
        MSM_DSI_PHY_28NM_HPM,
@@ -92,10 +93,6 @@ struct drm_bridge *msm_dsi_manager_bridge_init(u8 id);
 void msm_dsi_manager_bridge_destroy(struct drm_bridge *bridge);
 struct drm_connector *msm_dsi_manager_connector_init(u8 id);
 struct drm_connector *msm_dsi_manager_ext_bridge_init(u8 id);
-int msm_dsi_manager_phy_enable(int id,
-               const unsigned long bit_rate, const unsigned long esc_rate,
-               struct msm_dsi_phy_shared_timings *shared_timing);
-void msm_dsi_manager_phy_disable(int id);
 int msm_dsi_manager_cmd_xfer(int id, const struct mipi_dsi_msg *msg);
 bool msm_dsi_manager_cmd_xfer_trigger(int id, u32 dma_base, u32 len);
 void msm_dsi_manager_attach_dsi_device(int id, u32 device_flags);
@@ -155,7 +152,8 @@ void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host,
                                        u32 dma_base, u32 len);
 int msm_dsi_host_enable(struct mipi_dsi_host *host);
 int msm_dsi_host_disable(struct mipi_dsi_host *host);
-int msm_dsi_host_power_on(struct mipi_dsi_host *host);
+int msm_dsi_host_power_on(struct mipi_dsi_host *host,
+                       struct msm_dsi_phy_shared_timings *phy_shared_timings);
 int msm_dsi_host_power_off(struct mipi_dsi_host *host);
 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
                                        struct drm_display_mode *mode);
@@ -167,6 +165,8 @@ void msm_dsi_host_unregister(struct mipi_dsi_host *host);
 int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
                        struct msm_dsi_pll *src_pll);
 void msm_dsi_host_reset_phy(struct mipi_dsi_host *host);
+void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host,
+       struct msm_dsi_phy_clk_request *clk_req);
 void msm_dsi_host_destroy(struct mipi_dsi_host *host);
 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
                                        struct drm_device *dev);
@@ -179,10 +179,16 @@ struct msm_dsi_phy_shared_timings {
        u32 clk_pre;
        bool clk_pre_inc_by_2;
 };
+
+struct msm_dsi_phy_clk_request {
+       unsigned long bitclk_rate;
+       unsigned long escclk_rate;
+};
+
 void msm_dsi_phy_driver_register(void);
 void msm_dsi_phy_driver_unregister(void);
 int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
-       const unsigned long bit_rate, const unsigned long esc_rate);
+                       struct msm_dsi_phy_clk_request *clk_req);
 void msm_dsi_phy_disable(struct msm_dsi_phy *phy);
 void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy,
                        struct msm_dsi_phy_shared_timings *shared_timing);

diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 1d2c9b46737d53a861acb57cb5b978f809e161d1..1fc07ce24686b372252a43d3b9984467fbff2c28 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -2128,6 +2128,15 @@ void msm_dsi_host_reset_phy(struct mipi_dsi_host *host)
        udelay(100);
 }
 
+void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host,
+       struct msm_dsi_phy_clk_request *clk_req)
+{
+       struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
+
+       clk_req->bitclk_rate = msm_host->byte_clk_rate * 8;
+       clk_req->escclk_rate = msm_host->esc_clk_rate;
+}
+
 int msm_dsi_host_enable(struct mipi_dsi_host *host)
 {
        struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
@@ -2175,10 +2184,10 @@ static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable)
                        SFPB_GPREG_MASTER_PORT_EN(en));
 }
 
-int msm_dsi_host_power_on(struct mipi_dsi_host *host)
+int msm_dsi_host_power_on(struct mipi_dsi_host *host,
+                       struct msm_dsi_phy_shared_timings *phy_shared_timings)
 {
        struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
-       struct msm_dsi_phy_shared_timings phy_shared_timings;
        int ret = 0;
 
        mutex_lock(&msm_host->dev_mutex);
@@ -2189,12 +2198,6 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host)
 
        msm_dsi_sfpb_config(msm_host, true);
 
-       ret = dsi_calc_clk_rate(msm_host);
-       if (ret) {
-               pr_err("%s: unable to calc clk rate, %d\n", __func__, ret);
-               goto unlock_ret;
-       }
-
        ret = dsi_host_regulator_enable(msm_host);
        if (ret) {
                pr_err("%s:Failed to enable vregs.ret=%d\n",
@@ -2202,22 +2205,6 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host)
                goto unlock_ret;
        }
 
-       ret = dsi_bus_clk_enable(msm_host);
-       if (ret) {
-               pr_err("%s: failed to enable bus clocks, %d\n", __func__, ret);
-               goto fail_disable_reg;
-       }
-
-       ret = msm_dsi_manager_phy_enable(msm_host->id,
-                                       msm_host->byte_clk_rate * 8,
-                                       msm_host->esc_clk_rate,
-                                       &phy_shared_timings);
-       dsi_bus_clk_disable(msm_host);
-       if (ret) {
-               pr_err("%s: failed to enable phy, %d\n", __func__, ret);
-               goto fail_disable_reg;
-       }
-
        ret = dsi_clk_ctrl(msm_host, 1);
        if (ret) {
                pr_err("%s: failed to enable clocks. ret=%d\n", __func__, ret);
@@ -2233,7 +2220,7 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host)
 
        dsi_timing_setup(msm_host);
        dsi_sw_reset(msm_host);
-       dsi_ctrl_config(msm_host, true, &phy_shared_timings);
+       dsi_ctrl_config(msm_host, true, phy_shared_timings);
 
        if (msm_host->disp_en_gpio)
                gpiod_set_value(msm_host->disp_en_gpio, 1);
@@ -2269,8 +2256,6 @@ int msm_dsi_host_power_off(struct mipi_dsi_host *host)
 
        pinctrl_pm_select_sleep_state(&msm_host->pdev->dev);
 
-       msm_dsi_manager_phy_disable(msm_host->id);
-
        dsi_clk_ctrl(msm_host, 0);
 
        dsi_host_regulator_disable(msm_host);
@@ -2290,6 +2275,7 @@ int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
                                        struct drm_display_mode *mode)
 {
        struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
+       int ret;
 
        if (msm_host->mode) {
                drm_mode_destroy(msm_host->dev, msm_host->mode);
@@ -2302,6 +2288,12 @@ int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
                return -ENOMEM;
        }
 
+       ret = dsi_calc_clk_rate(msm_host);
+       if (ret) {
+               pr_err("%s: unable to calc clk rate, %d\n", __func__, ret);
+               return ret;
+       }
+
        return 0;
 }
 

diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index cb67e78d775b487a856af05f15dfb4a0b30d9c97..921270ea6059debadab1a785ed19ca79b064811c 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -125,6 +125,84 @@ static int dsi_mgr_setup_components(int id)
        return ret;
 }
 
+static int enable_phy(struct msm_dsi *msm_dsi, int src_pll_id,
+                     struct msm_dsi_phy_shared_timings *shared_timings)
+{
+       struct msm_dsi_phy_clk_request clk_req;
+       int ret;
+
+       msm_dsi_host_get_phy_clk_req(msm_dsi->host, &clk_req);
+
+       ret = msm_dsi_phy_enable(msm_dsi->phy, src_pll_id, &clk_req);
+       msm_dsi_phy_get_shared_timings(msm_dsi->phy, shared_timings);
+
+       return ret;
+}
+
+static int
+dsi_mgr_phy_enable(int id,
+                  struct msm_dsi_phy_shared_timings shared_timings[DSI_MAX])
+{
+       struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id);
+       struct msm_dsi *mdsi = dsi_mgr_get_dsi(DSI_CLOCK_MASTER);
+       struct msm_dsi *sdsi = dsi_mgr_get_dsi(DSI_CLOCK_SLAVE);
+       int src_pll_id = IS_DUAL_DSI() ? DSI_CLOCK_MASTER : id;
+       int ret;
+
+       /* In case of dual DSI, some registers in PHY1 have been programmed
+        * during PLL0 clock's set_rate. The PHY1 reset called by host1 here
+        * will silently reset those PHY1 registers. Therefore we need to reset
+        * and enable both PHYs before any PLL clock operation.
+        */
+       if (IS_DUAL_DSI() && mdsi && sdsi) {
+               if (!mdsi->phy_enabled && !sdsi->phy_enabled) {
+                       msm_dsi_host_reset_phy(mdsi->host);
+                       msm_dsi_host_reset_phy(sdsi->host);
+
+                       ret = enable_phy(mdsi, src_pll_id,
+                                        &shared_timings[DSI_CLOCK_MASTER]);
+                       if (ret)
+                               return ret;
+                       ret = enable_phy(sdsi, src_pll_id,
+                                        &shared_timings[DSI_CLOCK_SLAVE]);
+                       if (ret) {
+                               msm_dsi_phy_disable(mdsi->phy);
+                               return ret;
+                       }
+               }
+       } else {
+               msm_dsi_host_reset_phy(mdsi->host);
+               ret = enable_phy(msm_dsi, src_pll_id, &shared_timings[id]);
+               if (ret)
+                       return ret;
+       }
+
+       msm_dsi->phy_enabled = true;
+
+       return 0;
+}
+
+static void dsi_mgr_phy_disable(int id)
+{
+       struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id);
+       struct msm_dsi *mdsi = dsi_mgr_get_dsi(DSI_CLOCK_MASTER);
+       struct msm_dsi *sdsi = dsi_mgr_get_dsi(DSI_CLOCK_SLAVE);
+
+       /* disable DSI phy
+        * In dual-dsi configuration, the phy should be disabled for the
+        * first controller only when the second controller is disabled.
+        */
+       msm_dsi->phy_enabled = false;
+       if (IS_DUAL_DSI() && mdsi && sdsi) {
+               if (!mdsi->phy_enabled && !sdsi->phy_enabled) {
+                       msm_dsi_phy_disable(sdsi->phy);
+                       msm_dsi_phy_disable(mdsi->phy);
+               }
+       } else {
+               msm_dsi_phy_disable(msm_dsi->phy);
+       }
+}
+
 struct dsi_connector {
        struct drm_connector base;
        int id;
@@ -360,22 +438,31 @@ static void dsi_mgr_bridge_pre_enable(struct drm_bridge *bridge)
        struct msm_dsi *msm_dsi1 = dsi_mgr_get_dsi(DSI_1);
        struct mipi_dsi_host *host = msm_dsi->host;
        struct drm_panel *panel = msm_dsi->panel;
+       struct msm_dsi_phy_shared_timings phy_shared_timings[DSI_MAX];
        bool is_dual_dsi = IS_DUAL_DSI();
        int ret;
 
        DBG("id=%d", id);
-       if (!msm_dsi_device_connected(msm_dsi) ||
-                       (is_dual_dsi && (DSI_1 == id)))
+       if (!msm_dsi_device_connected(msm_dsi))
                return;
 
-       ret = msm_dsi_host_power_on(host);
+       ret = dsi_mgr_phy_enable(id, phy_shared_timings);
+       if (ret)
+               goto phy_en_fail;
+
+       /* Do nothing with the host if it is DSI 1 in case of dual DSI */
+       if (is_dual_dsi && (DSI_1 == id))
+               return;
+
+       ret = msm_dsi_host_power_on(host, &phy_shared_timings[id]);
        if (ret) {
                pr_err("%s: power on host %d failed, %d\n", __func__, id, ret);
                goto host_on_fail;
        }
 
        if (is_dual_dsi && msm_dsi1) {
-               ret = msm_dsi_host_power_on(msm_dsi1->host);
+               ret = msm_dsi_host_power_on(msm_dsi1->host,
+                                           &phy_shared_timings[DSI_1]);
                if (ret) {
                        pr_err("%s: power on host1 failed, %d\n",
                                                        __func__, ret);
@@ -434,6 +521,8 @@ static void dsi_mgr_bridge_pre_enable(struct drm_bridge *bridge)
 host1_on_fail:
        msm_dsi_host_power_off(host);
 host_on_fail:
+       dsi_mgr_phy_disable(id);
+phy_en_fail:
        return;
 }
 
@@ -459,10 +548,17 @@ static void dsi_mgr_bridge_post_disable(struct drm_bridge *bridge)
 
        DBG("id=%d", id);
 
-       if (!msm_dsi_device_connected(msm_dsi) ||
-                       (is_dual_dsi && (DSI_1 == id)))
+       if (!msm_dsi_device_connected(msm_dsi))
                return;
 
+       /*
+        * Do nothing with the host if it is DSI 1 in case of dual DSI.
+        * It is safe to call dsi_mgr_phy_disable() here because a single PHY
+        * won't be diabled until both PHYs request disable.
+        */
+       if (is_dual_dsi && (DSI_1 == id))
+               goto disable_phy;
+
        if (panel) {
                ret = drm_panel_disable(panel);
                if (ret)
@@ -497,6 +593,9 @@ static void dsi_mgr_bridge_post_disable(struct drm_bridge *bridge)
                        pr_err("%s: host1 power off failed, %d\n",
                                                                __func__, ret);
        }
+
+disable_phy:
+       dsi_mgr_phy_disable(id);
 }
 
 static void dsi_mgr_bridge_mode_set(struct drm_bridge *bridge,
@@ -664,73 +763,6 @@ void msm_dsi_manager_bridge_destroy(struct drm_bridge *bridge)
 {
 }
 
-int msm_dsi_manager_phy_enable(int id,
-               const unsigned long bit_rate, const unsigned long esc_rate,
-               struct msm_dsi_phy_shared_timings *shared_timings)
-{
-       struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id);
-       struct msm_dsi *mdsi = dsi_mgr_get_dsi(DSI_CLOCK_MASTER);
-       struct msm_dsi *sdsi = dsi_mgr_get_dsi(DSI_CLOCK_SLAVE);
-       struct msm_dsi_phy *phy = msm_dsi->phy;
-       int src_pll_id = IS_DUAL_DSI() ? DSI_CLOCK_MASTER : id;
-       int ret;
-
-       /* In case of dual DSI, some registers in PHY1 have been programmed
-        * during PLL0 clock's set_rate. The PHY1 reset called by host1 here
-        * will silently reset those PHY1 registers. Therefore we need to reset
-        * and enable both PHYs before any PLL clock operation.
-        */
-       if (IS_DUAL_DSI() && mdsi && sdsi) {
-               if (!mdsi->phy_enabled && !sdsi->phy_enabled) {
-                       msm_dsi_host_reset_phy(mdsi->host);
-                       msm_dsi_host_reset_phy(sdsi->host);
-                       ret = msm_dsi_phy_enable(mdsi->phy, src_pll_id,
-                                                bit_rate, esc_rate);
-                       if (ret)
-                               return ret;
-                       ret = msm_dsi_phy_enable(sdsi->phy, src_pll_id,
-                                                bit_rate, esc_rate);
-                       if (ret) {
-                               msm_dsi_phy_disable(mdsi->phy);
-                               return ret;
-                       }
-               }
-       } else {
-               msm_dsi_host_reset_phy(msm_dsi->host);
-               ret = msm_dsi_phy_enable(msm_dsi->phy, src_pll_id, bit_rate,
-                                                               esc_rate);
-               if (ret)
-                       return ret;
-       }
-
-       msm_dsi->phy_enabled = true;
-       msm_dsi_phy_get_shared_timings(phy, shared_timings);
-
-       return 0;
-}
-
-void msm_dsi_manager_phy_disable(int id)
-{
-       struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id);
-       struct msm_dsi *mdsi = dsi_mgr_get_dsi(DSI_CLOCK_MASTER);
-       struct msm_dsi *sdsi = dsi_mgr_get_dsi(DSI_CLOCK_SLAVE);
-       struct msm_dsi_phy *phy = msm_dsi->phy;
-
-       /* disable DSI phy
-        * In dual-dsi configuration, the phy should be disabled for the
-        * first controller only when the second controller is disabled.
-        */
-       msm_dsi->phy_enabled = false;
-       if (IS_DUAL_DSI() && mdsi && sdsi) {
-               if (!mdsi->phy_enabled && !sdsi->phy_enabled) {
-                       msm_dsi_phy_disable(sdsi->phy);
-                       msm_dsi_phy_disable(mdsi->phy);
-               }
-       } else {
-               msm_dsi_phy_disable(phy);
-       }
-}
-
 int msm_dsi_manager_cmd_xfer(int id, const struct mipi_dsi_msg *msg)
 {
        struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id);

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 1021c1c572ca4d0d3a6a2e46f9a9bfe76c4d1e84..a761531ec04cfb6aa3cb4c7c850a3856ec732d4e 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -54,8 +54,10 @@ static void dsi_dphy_timing_calc_clk_zero(struct msm_dsi_dphy_timing *timing,
 }
 
 int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
-       const unsigned long bit_rate, const unsigned long esc_rate)
+                            struct msm_dsi_phy_clk_request *clk_req)
 {
+       const unsigned long bit_rate = clk_req->bitclk_rate;
+       const unsigned long esc_rate = clk_req->escclk_rate;
        s32 ui, lpx;
        s32 tmax, tmin;
        s32 pcnt0 = 10;
@@ -429,7 +431,7 @@ void __exit msm_dsi_phy_driver_unregister(void)
 }
 
 int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
-       const unsigned long bit_rate, const unsigned long esc_rate)
+                       struct msm_dsi_phy_clk_request *clk_req)
 {
        struct device *dev = &phy->pdev->dev;
        int ret;
@@ -437,18 +439,24 @@ int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
        if (!phy || !phy->cfg->ops.enable)
                return -EINVAL;
 
+       ret = dsi_phy_enable_resource(phy);
+       if (ret) {
+               dev_err(dev, "%s: resource enable failed, %d\n",
+                       __func__, ret);
+               goto res_en_fail;
+       }
+
        ret = dsi_phy_regulator_enable(phy);
        if (ret) {
                dev_err(dev, "%s: regulator enable failed, %d\n",
                        __func__, ret);
-               return ret;
+               goto reg_en_fail;
        }
 
-       ret = phy->cfg->ops.enable(phy, src_pll_id, bit_rate, esc_rate);
+       ret = phy->cfg->ops.enable(phy, src_pll_id, clk_req);
        if (ret) {
                dev_err(dev, "%s: phy enable failed, %d\n", __func__, ret);
-               dsi_phy_regulator_disable(phy);
-               return ret;
+               goto phy_en_fail;
        }
 
        /*
@@ -460,14 +468,22 @@ int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
        if (phy->usecase != MSM_DSI_PHY_SLAVE) {
                ret = msm_dsi_pll_restore_state(phy->pll);
                if (ret) {
-                       pr_err("%s: failed to restore pll state\n", __func__);
-                       if (phy->cfg->ops.disable)
-                               phy->cfg->ops.disable(phy);
-                       dsi_phy_regulator_disable(phy);
-                       return ret;
+                       dev_err(dev, "%s: failed to restore pll state, %d\n",
+                               __func__, ret);
+                       goto pll_restor_fail;
                }
        }
 
+       return 0;
+
+pll_restor_fail:
+       if (phy->cfg->ops.disable)
+               phy->cfg->ops.disable(phy);
+phy_en_fail:
+       dsi_phy_regulator_disable(phy);
+reg_en_fail:
+       dsi_phy_disable_resource(phy);
+res_en_fail:
        return ret;
 }
 
@@ -483,6 +499,7 @@ void msm_dsi_phy_disable(struct msm_dsi_phy *phy)
        phy->cfg->ops.disable(phy);
 
        dsi_phy_regulator_disable(phy);
+       dsi_phy_disable_resource(phy);
 }
 
 void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy,

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index e1057423fd21a547619df659a304aa88701678bb..6472b600ac4189dc77109998c3961ccb2c4bf3fb 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -24,7 +24,7 @@
 struct msm_dsi_phy_ops {
        int (*init) (struct msm_dsi_phy *phy);
        int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
-               const unsigned long bit_rate, const unsigned long esc_rate);
+                       struct msm_dsi_phy_clk_request *clk_req);
        void (*disable)(struct msm_dsi_phy *phy);
 };
 
@@ -88,7 +88,7 @@ struct msm_dsi_phy {
  * PHY internal functions
  */
 int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
-       const unsigned long bit_rate, const unsigned long esc_rate);
+       struct msm_dsi_phy_clk_request *clk_req);
 void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
                                u32 bit_mask);
 int msm_dsi_phy_init_common(struct msm_dsi_phy *phy);

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
index c4a7be5dee607621a2a45ef59947879b1242af58..1ca6c69516f57c5740055c6b66d2b4b26c18ff63 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
@@ -72,7 +72,7 @@ static void dsi_20nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable)
 }
 
 static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
-               const unsigned long bit_rate, const unsigned long esc_rate)
+                               struct msm_dsi_phy_clk_request *clk_req)
 {
        struct msm_dsi_dphy_timing *timing = &phy->timing;
        int i;
@@ -81,7 +81,7 @@ static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
 
        DBG("");
 
-       if (msm_dsi_dphy_timing_calc(timing, bit_rate, esc_rate)) {
+       if (msm_dsi_dphy_timing_calc(timing, clk_req)) {
                dev_err(&phy->pdev->dev,
                        "%s: D-PHY timing calculation failed\n", __func__);
                return -EINVAL;

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
index ea740c5fb23587a345f6536c1a3c94561a971a16..4972b52cbe447c2cb0083485aa51f6afe95ddec2 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
@@ -67,7 +67,7 @@ static void dsi_28nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable)
 }
 
 static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
-               const unsigned long bit_rate, const unsigned long esc_rate)
+                               struct msm_dsi_phy_clk_request *clk_req)
 {
        struct msm_dsi_dphy_timing *timing = &phy->timing;
        int i;
@@ -75,7 +75,7 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
 
        DBG("");
 
-       if (msm_dsi_dphy_timing_calc(timing, bit_rate, esc_rate)) {
+       if (msm_dsi_dphy_timing_calc(timing, clk_req)) {
                dev_err(&phy->pdev->dev,
                        "%s: D-PHY timing calculation failed\n", __func__);
                return -EINVAL;

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
index 9aff0ba069cc082055850f8433726484493df6b4..39800446349848dce6bbfc9d2808d2d615f4152c 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
@@ -124,14 +124,14 @@ static void dsi_28nm_phy_lane_config(struct msm_dsi_phy *phy)
 }
 
 static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
-               const unsigned long bit_rate, const unsigned long esc_rate)
+                               struct msm_dsi_phy_clk_request *clk_req)
 {
        struct msm_dsi_dphy_timing *timing = &phy->timing;
        void __iomem *base = phy->base;
 
        DBG("");
 
-       if (msm_dsi_dphy_timing_calc(timing, bit_rate, esc_rate)) {
+       if (msm_dsi_dphy_timing_calc(timing, clk_req)) {
                dev_err(&phy->pdev->dev,
                        "%s: D-PHY timing calculation failed\n", __func__);
                return -EINVAL;