net: stmmac: xgmac: Implement MMC counters

Implement the MMC counters feature in XGMAC core.

Signed-off-by: Jose Abreu <joabreu@synopsys.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
index 3174b701aa903f6b07f6267dbc4fac64cfc1c818..86a42bc39d215f4c13c79c8ba885de59b8277cb6 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h
@@ -84,6 +84,7 @@
 #define XGMAC_HWFEAT_AVSEL             BIT(11)
 #define XGMAC_HWFEAT_RAVSEL            BIT(10)
 #define XGMAC_HWFEAT_ARPOFFSEL         BIT(9)
+#define XGMAC_HWFEAT_MMCSEL            BIT(8)
 #define XGMAC_HWFEAT_MGKSEL            BIT(7)
 #define XGMAC_HWFEAT_RWKSEL            BIT(6)
 #define XGMAC_HWFEAT_GMIISEL           BIT(1)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
index a4f236e3593e7f9f2c4759a1abaf41c62cf9d830..0f1c772e892ac7f8570190db65dc6a9b618ba799 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c
@@ -356,6 +356,7 @@ static void dwxgmac2_get_hw_feature(void __iomem *ioaddr,
        dma_cap->atime_stamp = (hw_cap & XGMAC_HWFEAT_TSSEL) >> 12;
        dma_cap->av = (hw_cap & XGMAC_HWFEAT_AVSEL) >> 11;
        dma_cap->av &= (hw_cap & XGMAC_HWFEAT_RAVSEL) >> 10;
+       dma_cap->rmon = (hw_cap & XGMAC_HWFEAT_MMCSEL) >> 8;
        dma_cap->pmt_magic_frame = (hw_cap & XGMAC_HWFEAT_MGKSEL) >> 7;
        dma_cap->pmt_remote_wake_up = (hw_cap & XGMAC_HWFEAT_RWKSEL) >> 6;
        dma_cap->mbps_1000 = (hw_cap & XGMAC_HWFEAT_GMIISEL) >> 1;

diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.c b/drivers/net/ethernet/stmicro/stmmac/hwif.c
index 6c61b753b55e3d777ea4804c5c4e24477499a6ee..3af2e5015245dac2f5320c1ed9952e7e8fcdd471 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/hwif.c
+++ b/drivers/net/ethernet/stmicro/stmmac/hwif.c
@@ -201,7 +201,7 @@ static const struct stmmac_hwif_entry {
                .min_id = DWXGMAC_CORE_2_10,
                .regs = {
                        .ptp_off = PTP_XGMAC_OFFSET,
-                       .mmc_off = 0,
+                       .mmc_off = MMC_XGMAC_OFFSET,
                },
                .desc = &dwxgmac210_desc_ops,
                .dma = &dwxgmac210_dma_ops,
@@ -209,7 +209,7 @@ static const struct stmmac_hwif_entry {
                .hwtimestamp = &stmmac_ptp,
                .mode = NULL,
                .tc = &dwmac510_tc_ops,
-               .mmc = NULL,
+               .mmc = &dwxgmac_mmc_ops,
                .setup = dwxgmac2_setup,
                .quirks = NULL,
        },

diff --git a/drivers/net/ethernet/stmicro/stmmac/hwif.h b/drivers/net/ethernet/stmicro/stmmac/hwif.h
index 278c0dbec9d9c51fc7bf65400d6fbddac549a972..00539a09d1db96299f99b739bb3e56943b7d5b25 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/hwif.h
+++ b/drivers/net/ethernet/stmicro/stmmac/hwif.h
@@ -503,6 +503,7 @@ extern const struct stmmac_ops dwxgmac210_ops;
 extern const struct stmmac_dma_ops dwxgmac210_dma_ops;
 extern const struct stmmac_desc_ops dwxgmac210_desc_ops;
 extern const struct stmmac_mmc_ops dwmac_mmc_ops;
+extern const struct stmmac_mmc_ops dwxgmac_mmc_ops;
 
 #define GMAC_VERSION           0x00000020      /* GMAC CORE Version */
 #define GMAC4_VERSION          0x00000110      /* GMAC4+ CORE Version */

diff --git a/drivers/net/ethernet/stmicro/stmmac/mmc.h b/drivers/net/ethernet/stmicro/stmmac/mmc.h
index 3587ceb9faf5525dda48e153c834f1dbb3919b9a..a0c05925883e49e8251d6b446594b576ddeaa73a 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/mmc.h
+++ b/drivers/net/ethernet/stmicro/stmmac/mmc.h
@@ -24,6 +24,7 @@
 
 #define MMC_GMAC4_OFFSET               0x700
 #define MMC_GMAC3_X_OFFSET             0x100
+#define MMC_XGMAC_OFFSET               0x800
 
 struct stmmac_counters {
        unsigned int mmc_tx_octetcount_gb;
@@ -116,6 +117,14 @@ struct stmmac_counters {
        unsigned int mmc_rx_tcp_err_octets;
        unsigned int mmc_rx_icmp_gd_octets;
        unsigned int mmc_rx_icmp_err_octets;
+
+       /* FPE */
+       unsigned int mmc_tx_fpe_fragment_cntr;
+       unsigned int mmc_tx_hold_req_cntr;
+       unsigned int mmc_rx_packet_assembly_err_cntr;
+       unsigned int mmc_rx_packet_smd_err_cntr;
+       unsigned int mmc_rx_packet_assembly_ok_cntr;
+       unsigned int mmc_rx_fpe_fragment_cntr;
 };
 
 #endif /* __MMC_H__ */

diff --git a/drivers/net/ethernet/stmicro/stmmac/mmc_core.c b/drivers/net/ethernet/stmicro/stmmac/mmc_core.c
index a471db6d7b110a7edcfee755c510124f5efa0cbf..a223584f5f9a67da9ea7492a63c3f57cef08fd40 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/mmc_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/mmc_core.c
@@ -119,6 +119,64 @@
 #define MMC_RX_ICMP_GD_OCTETS          0x180
 #define MMC_RX_ICMP_ERR_OCTETS         0x184
 
+/* XGMAC MMC Registers */
+#define MMC_XGMAC_TX_OCTET_GB          0x14
+#define MMC_XGMAC_TX_PKT_GB            0x1c
+#define MMC_XGMAC_TX_BROAD_PKT_G       0x24
+#define MMC_XGMAC_TX_MULTI_PKT_G       0x2c
+#define MMC_XGMAC_TX_64OCT_GB          0x34
+#define MMC_XGMAC_TX_65OCT_GB          0x3c
+#define MMC_XGMAC_TX_128OCT_GB         0x44
+#define MMC_XGMAC_TX_256OCT_GB         0x4c
+#define MMC_XGMAC_TX_512OCT_GB         0x54
+#define MMC_XGMAC_TX_1024OCT_GB                0x5c
+#define MMC_XGMAC_TX_UNI_PKT_GB                0x64
+#define MMC_XGMAC_TX_MULTI_PKT_GB      0x6c
+#define MMC_XGMAC_TX_BROAD_PKT_GB      0x74
+#define MMC_XGMAC_TX_UNDER             0x7c
+#define MMC_XGMAC_TX_OCTET_G           0x84
+#define MMC_XGMAC_TX_PKT_G             0x8c
+#define MMC_XGMAC_TX_PAUSE             0x94
+#define MMC_XGMAC_TX_VLAN_PKT_G                0x9c
+#define MMC_XGMAC_TX_LPI_USEC          0xa4
+#define MMC_XGMAC_TX_LPI_TRAN          0xa8
+
+#define MMC_XGMAC_RX_PKT_GB            0x100
+#define MMC_XGMAC_RX_OCTET_GB          0x108
+#define MMC_XGMAC_RX_OCTET_G           0x110
+#define MMC_XGMAC_RX_BROAD_PKT_G       0x118
+#define MMC_XGMAC_RX_MULTI_PKT_G       0x120
+#define MMC_XGMAC_RX_CRC_ERR           0x128
+#define MMC_XGMAC_RX_RUNT_ERR          0x130
+#define MMC_XGMAC_RX_JABBER_ERR                0x134
+#define MMC_XGMAC_RX_UNDER             0x138
+#define MMC_XGMAC_RX_OVER              0x13c
+#define MMC_XGMAC_RX_64OCT_GB          0x140
+#define MMC_XGMAC_RX_65OCT_GB          0x148
+#define MMC_XGMAC_RX_128OCT_GB         0x150
+#define MMC_XGMAC_RX_256OCT_GB         0x158
+#define MMC_XGMAC_RX_512OCT_GB         0x160
+#define MMC_XGMAC_RX_1024OCT_GB                0x168
+#define MMC_XGMAC_RX_UNI_PKT_G         0x170
+#define MMC_XGMAC_RX_LENGTH_ERR                0x178
+#define MMC_XGMAC_RX_RANGE             0x180
+#define MMC_XGMAC_RX_PAUSE             0x188
+#define MMC_XGMAC_RX_FIFOOVER_PKT      0x190
+#define MMC_XGMAC_RX_VLAN_PKT_GB       0x198
+#define MMC_XGMAC_RX_WATCHDOG_ERR      0x1a0
+#define MMC_XGMAC_RX_LPI_USEC          0x1a4
+#define MMC_XGMAC_RX_LPI_TRAN          0x1a8
+#define MMC_XGMAC_RX_DISCARD_PKT_GB    0x1ac
+#define MMC_XGMAC_RX_DISCARD_OCT_GB    0x1b4
+#define MMC_XGMAC_RX_ALIGN_ERR_PKT     0x1bc
+
+#define MMC_XGMAC_TX_FPE_FRAG          0x208
+#define MMC_XGMAC_TX_HOLD_REQ          0x20c
+#define MMC_XGMAC_RX_PKT_ASSEMBLY_ERR  0x228
+#define MMC_XGMAC_RX_PKT_SMD_ERR       0x22c
+#define MMC_XGMAC_RX_PKT_ASSEMBLY_OK   0x230
+#define MMC_XGMAC_RX_FPE_FRAG          0x234
+
 static void dwmac_mmc_ctrl(void __iomem *mmcaddr, unsigned int mode)
 {
        u32 value = readl(mmcaddr + MMC_CNTRL);
@@ -263,3 +321,137 @@ const struct stmmac_mmc_ops dwmac_mmc_ops = {
        .intr_all_mask = dwmac_mmc_intr_all_mask,
        .read = dwmac_mmc_read,
 };
+
+static void dwxgmac_mmc_ctrl(void __iomem *mmcaddr, unsigned int mode)
+{
+       u32 value = readl(mmcaddr + MMC_CNTRL);
+
+       value |= (mode & 0x3F);
+
+       writel(value, mmcaddr + MMC_CNTRL);
+}
+
+static void dwxgmac_mmc_intr_all_mask(void __iomem *mmcaddr)
+{
+       writel(MMC_DEFAULT_MASK, mmcaddr + MMC_RX_INTR_MASK);
+       writel(MMC_DEFAULT_MASK, mmcaddr + MMC_TX_INTR_MASK);
+}
+
+static void dwxgmac_read_mmc_reg(void __iomem *addr, u32 reg, u32 *dest)
+{
+       u64 tmp = 0;
+
+       tmp += readl(addr + reg);
+       tmp += ((u64 )readl(addr + reg + 0x4)) << 32;
+       if (tmp > GENMASK(31, 0))
+               *dest = ~0x0;
+       else
+               *dest = *dest + tmp;
+}
+
+/* This reads the MAC core counters (if actaully supported).
+ * by default the MMC core is programmed to reset each
+ * counter after a read. So all the field of the mmc struct
+ * have to be incremented.
+ */
+static void dwxgmac_mmc_read(void __iomem *mmcaddr, struct stmmac_counters *mmc)
+{
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_OCTET_GB,
+                            &mmc->mmc_tx_octetcount_gb);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_PKT_GB,
+                            &mmc->mmc_tx_framecount_gb);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_BROAD_PKT_G,
+                            &mmc->mmc_tx_broadcastframe_g);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_MULTI_PKT_G,
+                            &mmc->mmc_tx_multicastframe_g);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_64OCT_GB,
+                            &mmc->mmc_tx_64_octets_gb);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_65OCT_GB,
+                            &mmc->mmc_tx_65_to_127_octets_gb);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_128OCT_GB,
+                            &mmc->mmc_tx_128_to_255_octets_gb);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_256OCT_GB,
+                            &mmc->mmc_tx_256_to_511_octets_gb);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_512OCT_GB,
+                            &mmc->mmc_tx_512_to_1023_octets_gb);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_1024OCT_GB,
+                            &mmc->mmc_tx_1024_to_max_octets_gb);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_UNI_PKT_GB,
+                            &mmc->mmc_tx_unicast_gb);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_MULTI_PKT_GB,
+                            &mmc->mmc_tx_multicast_gb);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_BROAD_PKT_GB,
+                            &mmc->mmc_tx_broadcast_gb);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_UNDER,
+                            &mmc->mmc_tx_underflow_error);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_OCTET_G,
+                            &mmc->mmc_tx_octetcount_g);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_PKT_G,
+                            &mmc->mmc_tx_framecount_g);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_PAUSE,
+                            &mmc->mmc_tx_pause_frame);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_TX_VLAN_PKT_G,
+                            &mmc->mmc_tx_vlan_frame_g);
+
+       /* MMC RX counter registers */
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_PKT_GB,
+                            &mmc->mmc_rx_framecount_gb);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_OCTET_GB,
+                            &mmc->mmc_rx_octetcount_gb);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_OCTET_G,
+                            &mmc->mmc_rx_octetcount_g);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_BROAD_PKT_G,
+                            &mmc->mmc_rx_broadcastframe_g);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_MULTI_PKT_G,
+                            &mmc->mmc_rx_multicastframe_g);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_CRC_ERR,
+                            &mmc->mmc_rx_crc_error);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_CRC_ERR,
+                            &mmc->mmc_rx_crc_error);
+       mmc->mmc_rx_run_error += readl(mmcaddr + MMC_XGMAC_RX_RUNT_ERR);
+       mmc->mmc_rx_jabber_error += readl(mmcaddr + MMC_XGMAC_RX_JABBER_ERR);
+       mmc->mmc_rx_undersize_g += readl(mmcaddr + MMC_XGMAC_RX_UNDER);
+       mmc->mmc_rx_oversize_g += readl(mmcaddr + MMC_XGMAC_RX_OVER);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_64OCT_GB,
+                            &mmc->mmc_rx_64_octets_gb);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_65OCT_GB,
+                            &mmc->mmc_rx_65_to_127_octets_gb);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_128OCT_GB,
+                            &mmc->mmc_rx_128_to_255_octets_gb);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_256OCT_GB,
+                            &mmc->mmc_rx_256_to_511_octets_gb);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_512OCT_GB,
+                            &mmc->mmc_rx_512_to_1023_octets_gb);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_1024OCT_GB,
+                            &mmc->mmc_rx_1024_to_max_octets_gb);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_UNI_PKT_G,
+                            &mmc->mmc_rx_unicast_g);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_LENGTH_ERR,
+                            &mmc->mmc_rx_length_error);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_RANGE,
+                            &mmc->mmc_rx_autofrangetype);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_PAUSE,
+                            &mmc->mmc_rx_pause_frames);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_FIFOOVER_PKT,
+                            &mmc->mmc_rx_fifo_overflow);
+       dwxgmac_read_mmc_reg(mmcaddr, MMC_XGMAC_RX_VLAN_PKT_GB,
+                            &mmc->mmc_rx_vlan_frames_gb);
+       mmc->mmc_rx_watchdog_error += readl(mmcaddr + MMC_XGMAC_RX_WATCHDOG_ERR);
+
+       mmc->mmc_tx_fpe_fragment_cntr += readl(mmcaddr + MMC_XGMAC_TX_FPE_FRAG);
+       mmc->mmc_tx_hold_req_cntr += readl(mmcaddr + MMC_XGMAC_TX_HOLD_REQ);
+       mmc->mmc_rx_packet_assembly_err_cntr +=
+               readl(mmcaddr + MMC_XGMAC_RX_PKT_ASSEMBLY_ERR);
+       mmc->mmc_rx_packet_smd_err_cntr +=
+               readl(mmcaddr + MMC_XGMAC_RX_PKT_SMD_ERR);
+       mmc->mmc_rx_packet_assembly_ok_cntr +=
+               readl(mmcaddr + MMC_XGMAC_RX_PKT_ASSEMBLY_OK);
+       mmc->mmc_rx_fpe_fragment_cntr +=
+               readl(mmcaddr + MMC_XGMAC_RX_FPE_FRAG);
+}
+
+const struct stmmac_mmc_ops dwxgmac_mmc_ops = {
+       .ctrl = dwxgmac_mmc_ctrl,
+       .intr_all_mask = dwxgmac_mmc_intr_all_mask,
+       .read = dwxgmac_mmc_read,
+};

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
index 6efb66820d4cb40dec095e43e633f8abbd772faa..d294590cba272c3dafa3fdc405845fecb26f825a 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
@@ -243,6 +243,12 @@ static const struct stmmac_stats stmmac_mmc[] = {
        STMMAC_MMC_STAT(mmc_rx_tcp_err_octets),
        STMMAC_MMC_STAT(mmc_rx_icmp_gd_octets),
        STMMAC_MMC_STAT(mmc_rx_icmp_err_octets),
+       STMMAC_MMC_STAT(mmc_tx_fpe_fragment_cntr),
+       STMMAC_MMC_STAT(mmc_tx_hold_req_cntr),
+       STMMAC_MMC_STAT(mmc_rx_packet_assembly_err_cntr),
+       STMMAC_MMC_STAT(mmc_rx_packet_smd_err_cntr),
+       STMMAC_MMC_STAT(mmc_rx_packet_assembly_ok_cntr),
+       STMMAC_MMC_STAT(mmc_rx_fpe_fragment_cntr),
 };
 #define STMMAC_MMC_STATS_LEN ARRAY_SIZE(stmmac_mmc)