drm/sun4i: sun8i-csc: Add support for color encoding and range

Conversion from YUV to RGB depends on range (limited or full) and
encoding (BT.601 or BT.709). Current code doesn't consider this and
always uses BT.601 encoding and limited range.

Fix this by introducing new CSC matrices, which are selected based on
range and encoding parameters.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190713120346.30349-4-jernej.skrabec@siol.net

diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c
index d0dd3edf1e2e0d56ba05078a81a1b94bf9fbc9c1..781955dd4995d4add13845c4c40a2158ab151121 100644 (file)
--- a/drivers/gpu/drm/sun4i/sun8i_csc.c
+++ b/drivers/gpu/drm/sun4i/sun8i_csc.c
@@ -18,16 +18,59 @@ static const u32 ccsc_base[2][2] = {
  * First tree values in each line are multiplication factor and last
  * value is constant, which is added at the end.
  */
-static const u32 yuv2rgb[] = {
-       0x000004A8, 0x00000000, 0x00000662, 0xFFFC845A,
-       0x000004A8, 0xFFFFFE6F, 0xFFFFFCBF, 0x00021DF4,
-       0x000004A8, 0x00000813, 0x00000000, 0xFFFBAC4A,
+
+static const u32 yuv2rgb[2][2][12] = {
+       [DRM_COLOR_YCBCR_LIMITED_RANGE] = {
+               [DRM_COLOR_YCBCR_BT601] = {
+                       0x000004A8, 0x00000000, 0x00000662, 0xFFFC8451,
+                       0x000004A8, 0xFFFFFE6F, 0xFFFFFCC0, 0x00021E4D,
+                       0x000004A8, 0x00000811, 0x00000000, 0xFFFBACA9,
+               },
+               [DRM_COLOR_YCBCR_BT709] = {
+                       0x000004A8, 0x00000000, 0x0000072B, 0xFFFC1F99,
+                       0x000004A8, 0xFFFFFF26, 0xFFFFFDDF, 0x00013383,
+                       0x000004A8, 0x00000873, 0x00000000, 0xFFFB7BEF,
+               }
+       },
+       [DRM_COLOR_YCBCR_FULL_RANGE] = {
+               [DRM_COLOR_YCBCR_BT601] = {
+                       0x00000400, 0x00000000, 0x0000059B, 0xFFFD322E,
+                       0x00000400, 0xFFFFFEA0, 0xFFFFFD25, 0x00021DD5,
+                       0x00000400, 0x00000716, 0x00000000, 0xFFFC74BD,
+               },
+               [DRM_COLOR_YCBCR_BT709] = {
+                       0x00000400, 0x00000000, 0x0000064C, 0xFFFCD9B4,
+                       0x00000400, 0xFFFFFF41, 0xFFFFFE21, 0x00014F96,
+                       0x00000400, 0x0000076C, 0x00000000, 0xFFFC49EF,
+               }
+       },
 };
 
-static const u32 yvu2rgb[] = {
-       0x000004A8, 0x00000662, 0x00000000, 0xFFFC845A,
-       0x000004A8, 0xFFFFFCBF, 0xFFFFFE6F, 0x00021DF4,
-       0x000004A8, 0x00000000, 0x00000813, 0xFFFBAC4A,
+static const u32 yvu2rgb[2][2][12] = {
+       [DRM_COLOR_YCBCR_LIMITED_RANGE] = {
+               [DRM_COLOR_YCBCR_BT601] = {
+                       0x000004A8, 0x00000662, 0x00000000, 0xFFFC8451,
+                       0x000004A8, 0xFFFFFCC0, 0xFFFFFE6F, 0x00021E4D,
+                       0x000004A8, 0x00000000, 0x00000811, 0xFFFBACA9,
+               },
+               [DRM_COLOR_YCBCR_BT709] = {
+                       0x000004A8, 0x0000072B, 0x00000000, 0xFFFC1F99,
+                       0x000004A8, 0xFFFFFDDF, 0xFFFFFF26, 0x00013383,
+                       0x000004A8, 0x00000000, 0x00000873, 0xFFFB7BEF,
+               }
+       },
+       [DRM_COLOR_YCBCR_FULL_RANGE] = {
+               [DRM_COLOR_YCBCR_BT601] = {
+                       0x00000400, 0x0000059B, 0x00000000, 0xFFFD322E,
+                       0x00000400, 0xFFFFFD25, 0xFFFFFEA0, 0x00021DD5,
+                       0x00000400, 0x00000000, 0x00000716, 0xFFFC74BD,
+               },
+               [DRM_COLOR_YCBCR_BT709] = {
+                       0x00000400, 0x0000064C, 0x00000000, 0xFFFCD9B4,
+                       0x00000400, 0xFFFFFE21, 0xFFFFFF41, 0x00014F96,
+                       0x00000400, 0x00000000, 0x0000076C, 0xFFFC49EF,
+               }
+       },
 };
 
 /*
@@ -53,30 +96,74 @@ static const u32 yvu2rgb[] = {
  * c20 c21 c22 [d2 const2]
  */
 
-static const u32 yuv2rgb_de3[] = {
-       0x0002542a, 0x00000000, 0x0003312a, 0xffc00000,
-       0x0002542a, 0xffff376b, 0xfffe5fc3, 0xfe000000,
-       0x0002542a, 0x000408d3, 0x00000000, 0xfe000000,
+static const u32 yuv2rgb_de3[2][2][12] = {
+       [DRM_COLOR_YCBCR_LIMITED_RANGE] = {
+               [DRM_COLOR_YCBCR_BT601] = {
+                       0x0002542A, 0x00000000, 0x0003312A, 0xFFC00000,
+                       0x0002542A, 0xFFFF376B, 0xFFFE5FC3, 0xFE000000,
+                       0x0002542A, 0x000408D2, 0x00000000, 0xFE000000,
+               },
+               [DRM_COLOR_YCBCR_BT709] = {
+                       0x0002542A, 0x00000000, 0x000395E2, 0xFFC00000,
+                       0x0002542A, 0xFFFF92D2, 0xFFFEEF27, 0xFE000000,
+                       0x0002542A, 0x0004398C, 0x00000000, 0xFE000000,
+               }
+       },
+       [DRM_COLOR_YCBCR_FULL_RANGE] = {
+               [DRM_COLOR_YCBCR_BT601] = {
+                       0x00020000, 0x00000000, 0x0002CDD2, 0x00000000,
+                       0x00020000, 0xFFFF4FCE, 0xFFFE925D, 0xFE000000,
+                       0x00020000, 0x00038B43, 0x00000000, 0xFE000000,
+               },
+               [DRM_COLOR_YCBCR_BT709] = {
+                       0x00020000, 0x00000000, 0x0003264C, 0x00000000,
+                       0x00020000, 0xFFFFA018, 0xFFFF1053, 0xFE000000,
+                       0x00020000, 0x0003B611, 0x00000000, 0xFE000000,
+               }
+       },
 };
 
-static const u32 yvu2rgb_de3[] = {
-       0x0002542a, 0x0003312a, 0x00000000, 0xffc00000,
-       0x0002542a, 0xfffe5fc3, 0xffff376b, 0xfe000000,
-       0x0002542a, 0x00000000, 0x000408d3, 0xfe000000,
+static const u32 yvu2rgb_de3[2][2][12] = {
+       [DRM_COLOR_YCBCR_LIMITED_RANGE] = {
+               [DRM_COLOR_YCBCR_BT601] = {
+                       0x0002542A, 0x0003312A, 0x00000000, 0xFFC00000,
+                       0x0002542A, 0xFFFE5FC3, 0xFFFF376B, 0xFE000000,
+                       0x0002542A, 0x00000000, 0x000408D2, 0xFE000000,
+               },
+               [DRM_COLOR_YCBCR_BT709] = {
+                       0x0002542A, 0x000395E2, 0x00000000, 0xFFC00000,
+                       0x0002542A, 0xFFFEEF27, 0xFFFF92D2, 0xFE000000,
+                       0x0002542A, 0x00000000, 0x0004398C, 0xFE000000,
+               }
+       },
+       [DRM_COLOR_YCBCR_FULL_RANGE] = {
+               [DRM_COLOR_YCBCR_BT601] = {
+                       0x00020000, 0x0002CDD2, 0x00000000, 0x00000000,
+                       0x00020000, 0xFFFE925D, 0xFFFF4FCE, 0xFE000000,
+                       0x00020000, 0x00000000, 0x00038B43, 0xFE000000,
+               },
+               [DRM_COLOR_YCBCR_BT709] = {
+                       0x00020000, 0x0003264C, 0x00000000, 0x00000000,
+                       0x00020000, 0xFFFF1053, 0xFFFFA018, 0xFE000000,
+                       0x00020000, 0x00000000, 0x0003B611, 0xFE000000,
+               }
+       },
 };
 
 static void sun8i_csc_set_coefficients(struct regmap *map, u32 base,
-                                      enum sun8i_csc_mode mode)
+                                      enum sun8i_csc_mode mode,
+                                      enum drm_color_encoding encoding,
+                                      enum drm_color_range range)
 {
        const u32 *table;
        u32 base_reg;
 
        switch (mode) {
        case SUN8I_CSC_MODE_YUV2RGB:
-               table = yuv2rgb;
+               table = yuv2rgb[range][encoding];
                break;
        case SUN8I_CSC_MODE_YVU2RGB:
-               table = yvu2rgb;
+               table = yvu2rgb[range][encoding];
                break;
        default:
                DRM_WARN("Wrong CSC mode specified.\n");
@@ -88,17 +175,19 @@ static void sun8i_csc_set_coefficients(struct regmap *map, u32 base,
 }
 
 static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer,
-                                           enum sun8i_csc_mode mode)
+                                           enum sun8i_csc_mode mode,
+                                           enum drm_color_encoding encoding,
+                                           enum drm_color_range range)
 {
        const u32 *table;
        u32 base_reg;
 
        switch (mode) {
        case SUN8I_CSC_MODE_YUV2RGB:
-               table = yuv2rgb_de3;
+               table = yuv2rgb_de3[range][encoding];
                break;
        case SUN8I_CSC_MODE_YVU2RGB:
-               table = yvu2rgb_de3;
+               table = yvu2rgb_de3[range][encoding];
                break;
        default:
                DRM_WARN("Wrong CSC mode specified.\n");
@@ -137,19 +226,22 @@ static void sun8i_de3_ccsc_enable(struct regmap *map, int layer, bool enable)
 }
 
 void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer,
-                                    enum sun8i_csc_mode mode)
+                                    enum sun8i_csc_mode mode,
+                                    enum drm_color_encoding encoding,
+                                    enum drm_color_range range)
 {
        u32 base;
 
        if (mixer->cfg->is_de3) {
-               sun8i_de3_ccsc_set_coefficients(mixer->engine.regs,
-                                               layer, mode);
+               sun8i_de3_ccsc_set_coefficients(mixer->engine.regs, layer,
+                                               mode, encoding, range);
                return;
        }
 
        base = ccsc_base[mixer->cfg->ccsc][layer];
 
-       sun8i_csc_set_coefficients(mixer->engine.regs, base, mode);
+       sun8i_csc_set_coefficients(mixer->engine.regs, base,
+                                  mode, encoding, range);
 }
 
 void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable)

diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.h b/drivers/gpu/drm/sun4i/sun8i_csc.h
index dce4c444bcd625fe61abf5132484a7eaefdc5424..f42441b1b14ddfcc4bd8e82423365514b373d982 100644 (file)
--- a/drivers/gpu/drm/sun4i/sun8i_csc.h
+++ b/drivers/gpu/drm/sun4i/sun8i_csc.h
@@ -6,6 +6,8 @@
 #ifndef _SUN8I_CSC_H_
 #define _SUN8I_CSC_H_
 
+#include <drm/drm_color_mgmt.h>
+
 struct sun8i_mixer;
 
 /* VI channel CSC units offsets */
@@ -26,7 +28,9 @@ enum sun8i_csc_mode {
 };
 
 void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer,
-                                    enum sun8i_csc_mode mode);
+                                    enum sun8i_csc_mode mode,
+                                    enum drm_color_encoding encoding,
+                                    enum drm_color_range range);
 void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable);
 
 #endif

diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
index b227e33738f187cfbaf586980ca87b581e17473c..42d445d2377353cc0a7e1e3613cdd7edef3d3f49 100644 (file)
--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
@@ -231,7 +231,9 @@ static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel,
                           SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_MASK, val);
 
        if (fmt_info->csc != SUN8I_CSC_MODE_OFF) {
-               sun8i_csc_set_ccsc_coefficients(mixer, channel, fmt_info->csc);
+               sun8i_csc_set_ccsc_coefficients(mixer, channel, fmt_info->csc,
+                                               state->color_encoding,
+                                               state->color_range);
                sun8i_csc_enable_ccsc(mixer, channel, true);
        } else {
                sun8i_csc_enable_ccsc(mixer, channel, false);