drm/gf100-/gr: fetch tpcs-per-ppc info on startup

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/gk110b.c b/drivers/gpu/drm/nouveau/core/engine/graph/gk110b.c
index fe71375a57914610fb7ddb10e1428b1cde2b36d2..d07b19dc168d645889270fb17c24790647eb2b99 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/graph/gk110b.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/gk110b.c
@@ -113,4 +113,5 @@ gk110b_graph_oclass = &(struct nvc0_graph_oclass) {
        .mmio = gk110b_graph_pack_mmio,
        .fecs.ucode = &nvf0_graph_fecs_ucode,
        .gpccs.ucode = &nvf0_graph_gpccs_ucode,
+       .ppc_nr = 2,
 }.base;

diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/gk20a.c b/drivers/gpu/drm/nouveau/core/engine/graph/gk20a.c
index 74a51fc2ec8ac5beeee06d5fc8cf85afbb20a857..2420251ebc67c73f096c40602a450f2716d2b729 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/graph/gk20a.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/gk20a.c
@@ -44,4 +44,5 @@ gk20a_graph_oclass = &(struct nvc0_graph_oclass) {
        .cclass = &gk20a_grctx_oclass,
        .sclass = gk20a_graph_sclass,
        .mmio = nve4_graph_pack_mmio,
+       .ppc_nr = 1,
 }.base;

diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/gm107.c b/drivers/gpu/drm/nouveau/core/engine/graph/gm107.c
index 60d86f31428147842d1c988d6bfa59e1d747ce76..e20b98dbaf3e1e79c98c0d12923fb095ebea777b 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/graph/gm107.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/gm107.c
@@ -465,4 +465,5 @@ gm107_graph_oclass = &(struct nvc0_graph_oclass) {
        .mmio = gm107_graph_pack_mmio,
        .fecs.ucode = 0 ? &gm107_graph_fecs_ucode : NULL,
        .gpccs.ucode = &gm107_graph_gpccs_ucode,
+       .ppc_nr = 2,
 }.base;

diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv108.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv108.c
index 01e99faeb9a0e96efa4def85217a2795def7d425..2b0e8f48c02925f08b491973e3a9ec83ebcb985f 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv108.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv108.c
@@ -220,4 +220,5 @@ nv108_graph_oclass = &(struct nvc0_graph_oclass) {
        .mmio = nv108_graph_pack_mmio,
        .fecs.ucode = &nv108_graph_fecs_ucode,
        .gpccs.ucode = &nv108_graph_gpccs_ucode,
+       .ppc_nr = 1,
 }.base;

diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
index 0f984723734785b6ce26b13c4b227e2ca1c9f3d1..85d5c36c3f0a9407ebfcb94a586caec051ee6c0a 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
@@ -1503,7 +1503,7 @@ nvc0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
        struct nouveau_device *device = nv_device(parent);
        struct nvc0_graph_priv *priv;
        bool use_ext_fw, enable;
-       int ret, i;
+       int ret, i, j;
 
        use_ext_fw = nouveau_boolopt(device->cfgopt, "NvGrUseFW",
                                     oclass->fecs.ucode == NULL);
@@ -1549,6 +1549,11 @@ nvc0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
        for (i = 0; i < priv->gpc_nr; i++) {
                priv->tpc_nr[i]  = nv_rd32(priv, GPC_UNIT(i, 0x2608));
                priv->tpc_total += priv->tpc_nr[i];
+               priv->ppc_nr[i]  = oclass->ppc_nr;
+               for (j = 0; j < priv->ppc_nr[i]; j++) {
+                       u8 mask = nv_rd32(priv, GPC_UNIT(i, 0x0c30 + (j * 4)));
+                       priv->ppc_tpc_nr[i][j] = hweight8(mask);
+               }
        }
 
        /*XXX: these need figuring out... though it might not even matter */

diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
index fde401017556875ad67c3713b5c30c8dd1ef2fce..d520143681303de309e18b17236542a475624dd1 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
@@ -101,6 +101,8 @@ struct nvc0_graph_priv {
        u8 gpc_nr;
        u8 tpc_nr[GPC_MAX];
        u8 tpc_total;
+       u8 ppc_nr[GPC_MAX];
+       u8 ppc_tpc_nr[GPC_MAX][4];
 
        struct nouveau_gpuobj *unk4188b4;
        struct nouveau_gpuobj *unk4188b8;
@@ -189,6 +191,7 @@ struct nvc0_graph_oclass {
        struct {
                struct nvc0_graph_ucode *ucode;
        } gpccs;
+       int ppc_nr;
 };
 
 void nvc0_graph_mmio(struct nvc0_graph_priv *, const struct nvc0_graph_pack *);

diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c
index 2a6a94e2a0415e6aa19748e4aa461ab7061b2c00..41e8445c7eeaa81e69b5732027c84b19ce556b85 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c
@@ -133,4 +133,5 @@ nvd7_graph_oclass = &(struct nvc0_graph_oclass) {
        .mmio = nvd7_graph_pack_mmio,
        .fecs.ucode = &nvd7_graph_fecs_ucode,
        .gpccs.ucode = &nvd7_graph_gpccs_ucode,
+       .ppc_nr = 1,
 }.base;

diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c b/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c
index 9ba01fbb25576c9d0a3c0c94deb536bd448576b4..96c8d44e0f444e546fc685ab2f1b3bcaac9400e7 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c
@@ -343,4 +343,5 @@ nve4_graph_oclass = &(struct nvc0_graph_oclass) {
        .mmio = nve4_graph_pack_mmio,
        .fecs.ucode = &nve4_graph_fecs_ucode,
        .gpccs.ucode = &nve4_graph_gpccs_ucode,
+       .ppc_nr = 1,
 }.base;

diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c
index b82b40a1dc11f5b94f7c2dc78cfed2fe1a90d656..979ac8aa9a0342b7105574920105d3096e43c9d1 100644 (file)
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c
@@ -241,4 +241,5 @@ nvf0_graph_oclass = &(struct nvc0_graph_oclass) {
        .mmio = nvf0_graph_pack_mmio,
        .fecs.ucode = &nvf0_graph_fecs_ucode,
        .gpccs.ucode = &nvf0_graph_gpccs_ucode,
+       .ppc_nr = 2,
 }.base;