drm/amd/display: Fixed mpc add, enable always scaler for video surface.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
index 52f2f2dd9a434717d652a7dffd910cde952742dc..ce408ccb428ec886fcc6d8f70bfe9339f569af47 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
@@ -229,9 +229,9 @@ static void mpc10_mpcc_add(struct mpc *mpc, struct mpcc_cfg *cfg)
        mpc10_set_bg_color(mpc10, &cfg->black_color, mpcc_id);
 
        mpc10->mpcc_in_use_mask |= 1 << mpcc_id;
-       for (z_idx = cfg->z_index; z_idx < cfg->opp->mpc_tree.num_pipes; z_idx++) {
-               cfg->opp->mpc_tree.dpp[z_idx + 1] = cfg->opp->mpc_tree.dpp[z_idx];
-               cfg->opp->mpc_tree.mpcc[z_idx + 1] = cfg->opp->mpc_tree.mpcc[z_idx];
+       for (z_idx = cfg->opp->mpc_tree.num_pipes; z_idx > cfg->z_index; z_idx--) {
+               cfg->opp->mpc_tree.dpp[z_idx] = cfg->opp->mpc_tree.dpp[z_idx - 1];
+               cfg->opp->mpc_tree.mpcc[z_idx] = cfg->opp->mpc_tree.mpcc[z_idx - 1];
        }
        cfg->opp->mpc_tree.dpp[cfg->z_index] = cfg->mi->inst;
        cfg->opp->mpc_tree.mpcc[cfg->z_index] = mpcc_id;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index ee43cbc70c8a5c0213a1f49f6a62863f2859dda8..9c7ec047f083f49559cc39e68a2bafa53a2f8552 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -422,6 +422,10 @@ static const struct dc_debug debug_defaults_drv = {
                .force_abm_enable = false,
                .timing_trace = false,
                .clock_trace = true,
+               /* spread sheet doesn't handle taps_c is one properly,
+                * need to enable scaler for video surface to pass
+                * bandwidth validation.*/
+               .always_scale = true,
                .disable_pplib_clock_request = true,
                .disable_pplib_wm_range = false,
 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)