arm64: tegra: Fix AGIC register range

The Tegra AGIC interrupt controller is an ARM GIC400 interrupt
controller. Per the ARM GIC device-tree binding, the first address
region is for the GIC distributor registers and the second address
region is for the GIC CPU interface registers. The address space for
the distributor registers is 4kB, but currently this is incorrectly
defined as 8kB for the Tegra AGIC and overlaps with the CPU interface
registers. Correct the address space for the distributor to be 4kB.

Cc: stable@vger.kernel.org
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Fixes: bcdbde433542 ("arm64: tegra: Add AGIC node for Tegra210")
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index edf27fe2f10ee4bede489ca8d472001bb8c8278c..ec762b3455b4dd9b3e1b186885d84e4b720dbe29 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -1258,7 +1258,7 @@ agic: agic@702f9000 {
                        compatible = "nvidia,tegra210-agic";
                        #interrupt-cells = <3>;
                        interrupt-controller;
-                       reg = <0x702f9000 0x2000>,
+                       reg = <0x702f9000 0x1000>,
                              <0x702fa000 0x2000>;
                        interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
                        clocks = <&tegra_car TEGRA210_CLK_APE>;