]> asedeno.scripts.mit.edu Git - linux.git/commitdiff
clk: at91: optimize clk_round_rate() for AUDIO_PLL
authorMichał Mirosław <mirq-linux@rere.qmqm.pl>
Tue, 18 Dec 2018 11:20:48 +0000 (12:20 +0100)
committerStephen Boyd <sboyd@kernel.org>
Fri, 22 Feb 2019 17:54:17 +0000 (09:54 -0800)
Stop the search for parent rate when exact match is found.

This makes for 3 clk_round_rate() calls instead of 64 of them on
SAMA5D2-based board when searching for 12.288MHz clock.

Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Reviewed-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/at91/clk-audio-pll.c

index 36d77146a3bd428c3f42aa5b73c3e69253fd58ea..3cc4a82f4e9fba347e4cc1fa837d4722c7f75f36 100644 (file)
@@ -340,7 +340,12 @@ static long clk_audio_pll_pmc_round_rate(struct clk_hw *hw, unsigned long rate,
        pr_debug("A PLL/PMC: %s, rate = %lu (parent_rate = %lu)\n", __func__,
                 rate, *parent_rate);
 
-       for (div = 1; div <= AUDIO_PLL_QDPMC_MAX; div++) {
+       if (!rate)
+               return 0;
+
+       best_parent_rate = clk_round_rate(pclk->clk, 1);
+       div = max(best_parent_rate / rate, 1UL);
+       for (; div <= AUDIO_PLL_QDPMC_MAX; div++) {
                best_parent_rate = clk_round_rate(pclk->clk, rate * div);
                tmp_rate = best_parent_rate / div;
                tmp_diff = abs(rate - tmp_rate);
@@ -350,6 +355,8 @@ static long clk_audio_pll_pmc_round_rate(struct clk_hw *hw, unsigned long rate,
                        best_rate = tmp_rate;
                        best_diff = tmp_diff;
                        tmp_qd = div;
+                       if (!best_diff)
+                               break;  /* got exact match */
                }
        }