clk: renesas: r8a77965: Add FDP clock

This patch adds FDP1-0 clock to the R8A77965 SoC.

Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
index 312f9fe738e3b19d33bfd420ea0e90a5fd250bb8..1fcc411502da5e5f317c7f44a30d69b84d5cf2bf 100644 (file)
--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -112,6 +112,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
 };
 
 static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
+       DEF_MOD("fdp1-0",               119,    R8A77965_CLK_S0D1),
        DEF_MOD("scif5",                202,    R8A77965_CLK_S3D4),
        DEF_MOD("scif4",                203,    R8A77965_CLK_S3D4),
        DEF_MOD("scif3",                204,    R8A77965_CLK_S3D4),