arm64: dts: ls2088a: add pcie support

The physical memory map address and CCSR registers map address are
different between LS2088A and other LS2080A series SoCs.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
index 6aa319dae396ffffc135b4e9af9e893029dd1ba7..aeaef01d375fef26012341ba7e7c81e3ffcb47d9 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
@@ -151,6 +151,7 @@ CPU_PW20: cpu-pw20 {
 };
 
 &pcie1 {
+       compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
        reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
               0x20 0x00000000 0x0 0x00002000>; /* configuration space */
 
@@ -159,6 +160,7 @@ &pcie1 {
 };
 
 &pcie2 {
+       compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
        reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
               0x28 0x00000000 0x0 0x00002000>; /* configuration space */
 
@@ -167,6 +169,7 @@ &pcie2 {
 };
 
 &pcie3 {
+       compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
        reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
               0x30 0x00000000 0x0 0x00002000>; /* configuration space */
 
@@ -175,6 +178,7 @@ &pcie3 {
 };
 
 &pcie4 {
+       compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
        reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
               0x38 0x00000000 0x0 0x00002000>; /* configuration space */